US4870491A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Display control apparatus for supplying display data to raster scanning type display device
Assignee: Toshiba Corp
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Filing: 1986-05-15
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Granted: 1989-09-26
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Expires: 2006-05-15
Abstract
Abstract A video RAM write control circuit has a video RAM for storing pattern data of one frame at addresses thereof which correspond to display positions, and a control circuit for generating write pattern data and write addresses. The video RAM stores a pattern which is continuous in the horizontal direction, at consecutive addresses thereof. Each row on the screen consists of several rasters. A video RAM address has a memory address representing a position in the horizontal direction, in its lower bits, so well as a raster address representing a raster position of the row, at upper bits thereof. A write address is rotated toward the MSB by the number of bits of the raster address, and a resultant permuted address is supplied to the video RAM.
Inventors
- 👤 Takatoshi Ishii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:19
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
260 words
A display control apparatus for supplying dot data in synchronism with a timing of raster scanning to a display device of a raster scanning type for displaying a dot image, comprising: a video RAM for storing dot data corresponding to an image to be displayed on a screen of said display device, each storage location of said video RAM storing dot data for p dots, where p is a positive integer; control means for outputting write address data comprising lower q-bit memory addresses and higher r-bit raster addresses, to read out the dot data from said video RAM to be supplied to said display device, said memory addresses each indicating a position on the screen of a dot block including p x 2r dots, p dots in the horizontal direction X and 2r rasters in the vertical direction, said raster addresses each indicating a position of one of the rasters of a dot block; write means for supplying write addresses and the dot data to said video RAM; and addresses permuting means, receiving said write addresses from said write means and being selectively set in one of first and second modes, for supplying the write addresses to said video RAM without changes in the first mode, and for performing a bit permutation of said write addresses in said second mode and supplying lower r bits of the write addresses to said video RAM at the same bit positions as the raster addresses supplied from said control means to said video RAM and the bit-permuted write addresses to said video RAM.
Claim 2
Dependent Claim
260 words
A display control apparatus for supplying dot data in synchronism with a timing of raster scanning to a display device of a raster scanning type for displaying a dot image, comprising: a video RAM for storing dot data corresponding to an image to be displayed on a screen of said display device, each storage location of said video RAM storing dot data for p dots, where p is a positive integer; control means for outputting write address data comprising lower q-bit memory addresses and higher r-bit raster addresses, to read out the dot data from said video RAM to be supplied to said display device, said memory addresses each indicating a position on the screen of a dot block including p x 2r dots, p dots in the horizontal direction X and 2r rasters in the vertical direction, said raster addresses each indicating a position of one of the rasters of a dot block; write means for supplying write addresses and the dot data to said video RAM; and addresses permuting means, receiving said write addresses from said write means and being selectively set in one of first and second modes, for supplying the write addresses to said video RAM without changes in the first mode, and for performing a bit permutation of said write addresses in said second mode and supplying lower r bits of the write addresses to said video RAM at the same bit positions as the raster addresses supplied from said control means to said video RAM and the bit-permuted write addresses to said video RAM.
Claim 3
Dependent Claim
95 words
A display control apparatus according to claim 1, in which said address data supplied from said control means to said video RAM includes the q-bit memory addresses in a low-order position and the r-bit raster addresses in a high-order position, and said address permuting means shifts and rotates the write addresses in the least significant bit (LSB) direction so as to permute the lower r bit positions of the write addresses supplied from said write means into the upper r bits in the second mode and supplies the bit-permuted write addresses to said video RAM.
Claim 4
Dependent Claim
77 words
A display control apparatus according to claim 1, in which said address data supplied from said control means to said video RAM includes the q-bit memory addresses in a low-order position and the r-bit raster addresses in a high-order position, and said address permuting means permutes the lower r bits and the higher r-bits of the write addresses supplied from said write means and supplies the bit-permuted write addresses to said video RAM in the second mode.
Claim 5
Dependent Claim
92 words
A display control apparatus according to claim 1, in which the raster addresses generated by said control means are supplied to said video RAM so as to be interposed in the q-bit memory addresses, and said address permuting means performs bit-permutation so as to set the lower r bits of the write addresses generated from said write means to the same position as the raster addresses, which are interposed in the q-bit memory addresses, supplied from said control means to said video RAM, and supplies the bit-permuted addresses to said video RAM.
Claim 6
Dependent Claim
203 words
A write control apparatus for a video RAM which has a plurality of memory segments, the memory segments arranged in one horizontal line constituting a raster, 2 r rasters constituting a row, the memory segments in each raster being divided into a plurality of columns, memory segments included in one column and one row constituting a block of memory segments, each block of memory segments being designated by a memory address, each raster in one block of memory segments being designated by a raster address of r bits, comprising: means for generating a control address which is successively incremented; first converting means, connected to said generating means, for converting the control address into a first write address having a raster address and a memory address, said first converting means converting the lowest r bits of the control address into the raster address; second converting means, for converting the control address into a second write address having the raster address and the memory address, said second converting means converting the lowest r bits of the control address into the lowest r bits of the memory address; means for selectively supplying one of the first write address and the second address to the video RAM.
Claim 7
Dependent Claim
203 words
A write control apparatus for a video RAM which has a plurality of memory segments, the memory segments arranged in one horizontal line constituting a raster, 2 r rasters constituting a row, the memory segments in each raster being divided into a plurality of columns, memory segments included in one column and one row constituting a block of memory segments, each block of memory segments being designated by a memory address, each raster in one block of memory segments being designated by a raster address of r bits, comprising: means for generating a control address which is successively incremented; first converting means, connected to said generating means, for converting the control address into a first write address having a raster address and a memory address, said first converting means converting the lowest r bits of the control address into the raster address; second converting means, for converting the control address into a second write address having the raster address and the memory address, said second converting means converting the lowest r bits of the control address into the lowest r bits of the memory address; means for selectively supplying one of the first write address and the second address to the video RAM.
Claim 8
Dependent Claim
55 words
An apparatus according to claim 5, in which said first converting means converts remaining bits other than said lowest r bits of the control address into the memory address, and said second converting means converts r bits among said remaining bits other than said lowest r bits of the control address into the raster address.
Claim 9
Dependent Claim
28 words
An apparatus according to claim 5, in which each of said converting means and said second converting means comprise means for permutating the bits of the control address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |