US4870370A
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US
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Method and apparatus for two stage automatic gain control
Assignee: Teridian Semiconductor Corp
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Filing: 1988-02-19
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Granted: 1989-09-26
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Expires: 2008-02-19
Abstract
Abstract The present invention is a method and apparatus for implementing a two stage AGC circuit. In the preferred embodiment, the present invention is used as part of a receive channel in a modem. The first stage of the AGC is a "coarse" AGC and is used to track large signal transients of an input signal. The coarse AGC locks on to transient signals without excessive settling time. In operation, the coarse AGC acquires a new signal by using a nonlinear clipped feedback loop technique supported by a linearized feedback loop. The coarse AGC stage uses an error signal derived from the noncoherent power fluctuations of the incoming signal. The second stage of the AGC circuit is a "fine" AGC using a decision-directed coherent amplitude error signal and a quick linear feedback loop to correct for finer signal level fluctuations. The fine AGC has a high pass characteristic which decouples its response from that of the equalizer for stability reasons. The present invention avoids performance and response limitations of prior art AGC's in that the coarse stage is not required to have wide band response and associated noisy tracking response. Further, when the input signal is in quadrature amplitude modulation (QAM) the coarse stage tracks by using a nonlinear power detection algorithm which removes the effect of data power modulation. The fine AGC stage utilizes a decision-directed (coherent) error signal and a linear feedback loop with zero excess delay so that wideband response can be achieved without introducing amplitude modulation error in the signal path. As a result, the two stage scheme of the present invention can track rapid gain changes and restore correct data detection within a few baud, limiting error corruption to only one data block.
Inventors
- 👤 Dave Hedberg
- 👤 Chris Cole
- 👤 Steve Levy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:26
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3036; H03F; H03F2200/00; H03F2200/411
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
293 words
A circuit for controlling the gain of an input signal comprising: a first gain control stage coupled to said input signal for detecting an amplitude of said input signal, said first gain control stage for providing a first output signal having an amplitude within a first range; a second gain control stage coupled to said first output signal for detecting an amplitude of said first output signal, said second gain control stage for providing a second output signal having an amplitude within a second range; said first gain control stage comprising detection means for detecting the power level of said input signal, first comparing means for comparing said detected power level with a reference power level and for providing a first error signal, second comparing means coupled to said first error signal for providing a second error signal when said first error signal is within said first range, scaling means for converting said second error signal to a first gain scale factor, and first multiplying means for multiplying said input signal by said first gain scale factor; said second gain control stage comprising quantizing means coupled to said first output signal for quantizing said first output signal, third comparing means coupled to said quantized signal and said first output signal, said third comparing means for providing a third error signal representing a difference between said quantized signal and said first output signal, a first filter means coupled to said third error signal for scaling said third error signal to determine the sensitivity of said second gain control stage, said first filter means for providing a fourth error signal, second multiplying means coupled to said fourth error signal and said first output signal for multiplying said first output signal by said fourth error signal.
Claim 2
Dependent Claim
293 words
A circuit for controlling the gain of an input signal comprising: a first gain control stage coupled to said input signal for detecting an amplitude of said input signal, said first gain control stage for providing a first output signal having an amplitude within a first range; a second gain control stage coupled to said first output signal for detecting an amplitude of said first output signal, said second gain control stage for providing a second output signal having an amplitude within a second range; said first gain control stage comprising detection means for detecting the power level of said input signal, first comparing means for comparing said detected power level with a reference power level and for providing a first error signal, second comparing means coupled to said first error signal for providing a second error signal when said first error signal is within said first range, scaling means for converting said second error signal to a first gain scale factor, and first multiplying means for multiplying said input signal by said first gain scale factor; said second gain control stage comprising quantizing means coupled to said first output signal for quantizing said first output signal, third comparing means coupled to said quantized signal and said first output signal, said third comparing means for providing a third error signal representing a difference between said quantized signal and said first output signal, a first filter means coupled to said third error signal for scaling said third error signal to determine the sensitivity of said second gain control stage, said first filter means for providing a fourth error signal, second multiplying means coupled to said fourth error signal and said first output signal for multiplying said first output signal by said fourth error signal.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein said first range is greater than said second range.
Claim 4
Dependent Claim
47 words
The circuit of claim 1 wherein said detection means comprises first conversion means for converting said input signal into a complex signal having an inphase portion and a quadrature portion, and squaring means for squaring said complex signal to determine said power level of said complex signal.
Claim 5
Dependent Claim
21 words
The circuit of claim 1 wherein said quantizing means converts said first output signal to a quadrature amplitude modulation (QAM) constellation.
Claim 6
Dependent Claim
39 words
The circuit of claim 1 wherein said first filter means includes third multiplying means coupled to said third error signal and a second scaling factor and a low pass filter comprising integration means coupled to said third multiplying means.
Claim 7
Dependent Claim
323 words
A circuit for adjusting the amplitude of an analog input signal to a predetermined level comprising: a first gain control stage coupled to said analog input signal for detecting the amplitude of said input signal and for providing a first corrected signal having an amplitude within a first range; a second gain control stage coupled to said first gain control stage for detecting an amplitude of said first corrected signal, said second gain control stage for providing a second corrected signal having an amplitude within a second range; said first gain control stage comprising a first input means for receiving said analog input signal, first conversion means for converting said analog input signal to a digital signal, power detecting means for detecting a power level of said digital signal, first summing means coupled to said power detecting means and to a power reference level signal and for providing a first output signal representing the difference between said detected power level and said reference power level, first comparing means for providing a second output signal when said first output signal is outside a predetermined window, scaling means coupled to said second output signal for scaling said second output signal and for providing a third output signal representing a gain correction factor, first multiplying means for multiplying said analog input signal by said third output signal to correct the gain of said analog input signal; said second gain control stage comprising second input means for receiving said digital signal from said first gain control stage, second conversion means for generating a quantized output signal form said digital signal, second summing means for generating a difference signal between said digital signal and said quantized signal, first filter means coupled to said difference signal and for providing a fourth output signal representing a gain correction factor, second multiplying means for multiplying said digital signal by said fourth output signal to correct the gain of said digital signal.
Claim 8
Dependent Claim
323 words
A circuit for adjusting the amplitude of an analog input signal to a predetermined level comprising: a first gain control stage coupled to said analog input signal for detecting the amplitude of said input signal and for providing a first corrected signal having an amplitude within a first range; a second gain control stage coupled to said first gain control stage for detecting an amplitude of said first corrected signal, said second gain control stage for providing a second corrected signal having an amplitude within a second range; said first gain control stage comprising a first input means for receiving said analog input signal, first conversion means for converting said analog input signal to a digital signal, power detecting means for detecting a power level of said digital signal, first summing means coupled to said power detecting means and to a power reference level signal and for providing a first output signal representing the difference between said detected power level and said reference power level, first comparing means for providing a second output signal when said first output signal is outside a predetermined window, scaling means coupled to said second output signal for scaling said second output signal and for providing a third output signal representing a gain correction factor, first multiplying means for multiplying said analog input signal by said third output signal to correct the gain of said analog input signal; said second gain control stage comprising second input means for receiving said digital signal from said first gain control stage, second conversion means for generating a quantized output signal form said digital signal, second summing means for generating a difference signal between said digital signal and said quantized signal, first filter means coupled to said difference signal and for providing a fourth output signal representing a gain correction factor, second multiplying means for multiplying said digital signal by said fourth output signal to correct the gain of said digital signal.
Claim 9
Dependent Claim
32 words
The circuit of claim 6 wherein said first conversion means further includes means for converting said analog input signal to a complex digital word having an inphase portion and a quadrature portion.
Claim 10
Dependent Claim
34 words
The circuit of claim 7 wherein said second gain control stage further includes a second filter coupled to said difference signal for decoupling the second gain control stage from said first gain control stage.
Claim 11
Dependent Claim
15 words
The circuit of claim 6 wherein said predetermined window is plus or minus 3 decibels.
Claim 12
Dependent Claim
15 words
The circuit of claim 6 wherein said first filter means comprises a low pass filter.
Claim 13
Independent Claim
160 words
A method for adjusting the amplitude of an analog input signal comprising the steps of: determining a power level of said input signal and generating a power level signal; generating a first error signal representing a difference between said power level signal and a reference power level signal; determining if said first error signal is within a predetermined range; generating a first gain scale factor by multiplying said first error signal by a first scaling factor and multiplying said input signal by said first gain scale factor when said first error signal is not within said predetermined range; converting said input signal to a quantized signal; generating a second error signal representing a difference between said input signal and said quantized signal; generating a second gain scale factor by multiplying said second error signal by a second scaling factor and multiplying said input signal by said second gain scale factor when said first error signal is within said predetermined range.
Claim 14
Independent Claim
160 words
A method for adjusting the amplitude of an analog input signal comprising the steps of: determining a power level of said input signal and generating a power level signal; generating a first error signal representing a difference between said power level signal and a reference power level signal; determining if said first error signal is within a predetermined range; generating a first gain scale factor by multiplying said first error signal by a first scaling factor and multiplying said input signal by said first gain scale factor when said first error signal is not within said predetermined range; converting said input signal to a quantized signal; generating a second error signal representing a difference between said input signal and said quantized signal; generating a second gain scale factor by multiplying said second error signal by a second scaling factor and multiplying said input signal by said second gain scale factor when said first error signal is within said predetermined range.
Claim 15
Dependent Claim
44 words
The method of claim 11 wherein said step of determining a power level of said input signal is accomplished by converting said input signal to a complex digital signal having an inphase portion and a quadrature portion, and squaring said inphase and quadrature portions.
Claim 16
Dependent Claim
20 words
The method of claim 11 further including the step of filtering said second error signal with a low pass filter.
References Cited (Backward Citations)
US4213097A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |