Digital convergence circuit storing coefficients of fundamental waves of correction data

Claim 2

A digital convergence circuit comprising: coefficient storing means for storing weighting coefficients for each of a plurality of fundamental correction waves which have at least one of a horizontal scanning period and a vertical scanning period, said fundamental correction waves being waves which can be weighted by said weighting coefficients to form synthesized waves representative of correction data for correcting a deviation of a scanning line of said picture; controlling means, coupled to said coefficient storing means to receive said weighting coefficients, for forming correction data using said weighting coefficients and said fundamental correction waves; correction data storing means, connected to said coefficient storing means, for storing said correction data for each of a plurality of sampling points, said sampling points splitting said picture into a matrix; said controlling means also for reading said correction data from said correction data storing means in synchronism with a deflection scanning; and convergence deviation correction means, receiving said correction data read by said controlling means, for correcting a convergence deviation of a scanning line of a picture based on said correction data.

Claim 3

A circuit as in claim 1 further comprising memory means for determining and storing said plurality of fundamental correction waves.

Claim 4

A circuit as in claim 1 wherein said means for forming correction data includes means for adding said coefficients to said fundamental waves as a weighting function.

Claim 5

A circuit as in claim 2 wherein said fundamental correction waves include waves from the group consisting of: parabolic undulation waves having a vertical scanning period and a horizontal scanning period, serrated undulation waves, parabolic undulation waves which are amplitude-modulated by a serrated undulation wave and a serrated undulation wave which is amplitude-modulated by a parabolic undulation wave.

Claim 6

A circuit as in claim 1 wherein said correction data storing means stores said correction data at respective addresses therein, and said convergence circuit and further comprising address generating means for generating an address indicative of a location on the screen to address said correction data from said correction data storing means for said location on the screen.

Claim 7

A circuit as in claim 5 wherein said address generating means generates addresses in synchronism with a horizontal scan.

Claim 8

A circuit as in claim 6 further comprising timing generating means for generating timing pulses to determine a readout timing.

Claim 9

An apparatus as in claim 7 further comprising a phase-locked loop for setting a synchronization by synchronizing with a synchronization signal of the picture.

Claim 10

A digital convergence circuit comprising: correction data storing means for storing correction data for correcting a convergent deviation of a scanning line of a picture scan at addresses corresponding to locations in said picture; address generating means, coupled to said correction data storing means, for producing addresses to address said correction data in said correction data storing means beginning at a readout starting address, in synchronism with clock pulses obtained by multiplying frequencies of synchronization signals of said picture; and readout address controlling means, connected to said address generating means, for determining said readout starting address in accordance with a number of said scanning lines, so that a same correction data is obtained at a center of said picture scan independent of the number of said scanning lines, and thereby maintaining a vertical symmetry of said correction data.

Claim 11

A digital convergence circuit comprising: correction data storing means for storing correction data for correcting a convergent deviation of a scanning line of a picture scan at addresses corresponding to locations in said picture; address generating means, coupled to said correction data storing means, for producing addresses to address said correction data in said correction data storing means beginning at a readout starting address, in synchronism with clock pulses obtained by multiplying frequencies of synchronization signals of said picture; and readout address controlling means, connected to said address generating means, for determining said readout starting address in accordance with a number of said scanning lines, so that a same correction data is obtained at a center of said picture scan independent of the number of said scanning lines, and thereby maintaining a vertical symmetry of said correction data.

Claim 12

A circuit as in claim 9 wherein said correction data storing means is a digital circuit comprising: coefficient storing means for storing weighting coefficients for each of a plurality of fundamental correction waves which have at least one of a horizontal scanning period and a vertical scanning period, said fundamental correction waves being waves which can be weighted by said weighting coefficients to form synthesized waves representative of correction data for correcting a deviation of a scanning line of said picture; means coupled to said coefficient storing means to receive said weighting coefficients, for forming correction data using said weighting coefficients and said fundamental correction waves; correction data storing means connected to said coefficient storing means, for storing said correction data for each of a plurality of sampling points, said sampling points splitting said picture into a matrix; controlling means for reading said correction data from said correction data storing means in synchronism with a deflection scanning; and convergence deviation correction means, receiving said correction data read by said controlling means, for correcting a convergence deviation of a scanning line of a picture based on said correction data.

Claim 13

A circuit as in claim 9 wherein said synchronization signals are clock pulses, and further comprising clock pulse generating means for multiplying frequencies of said horizontal synchronization signals of said picture to produce said clock pulses.

Claim 14

An apparatus as in claim 10 wherein said fundamental correction waves include waves from the group consisting of: parabolic undulation waves having a vertical scanning period and a horizontal scanning period, serrated undulation waves, parabolic undulation waves which are amplitude-modulated by a serrated undulation wave and a serrated undulation wave which is amplitude-modulated by a parabolic undulation wave.

Claim 15

A circuit as in claim 10 wherein said correction data storing means stores said correction data at respective addresses therein, and further comprising address generating means for generating an address indicative of a location on the screen to address correction data from said correction data storing means for said location on the screen.

Claim 16

A circuit as in claim 13 further comprising input/output means for storing said readout starting address under control of said readout address controlling means.

Claim 17

A digital convergence circuit comprising: correction data storing means for storing correction data at respective addresses to correct a convergence deviation of a scanning line of a picture, said correction data storing means storing data for each of a plurality of sampling points which split said picture into a matrix; readout address generating means, connected to address said correction data storing means, for designating an address of said correction data storing means from which to read said correction data in accordance with clock pulses obtained by multiplying frequencies of synchronization signals; and central processing means for computing said correction data, and writing said data to said correction data storing means at addresses corresponding to locations on said picture, said central processing means including: (a) means for computing said correction data by using a correcting function which includes a coefficient that is variably set and a variable indicating a deflection scanning position when adjusting the convergence, (b) time division means for splitting one horizontal scanning period into a plurality of access periods, each shorter than said horizontal scanning period, said plurality of access periods corresponding to a number of said sampling points arranged in a horizontal direction of said picture scanning, and (c) means for dividing said access periods into a first period which is a time required to addressing by said readout address generating means, and a second access period of said central processing means to said correction data storing means.

Claim 18

A digital convergence circuit comprising: correction data storing means for storing correction data at respective addresses to correct a convergence deviation of a scanning line of a picture, said correction data storing means storing data for each of a plurality of sampling points which split said picture into a matrix; readout address generating means, connected to address said correction data storing means, for designating an address of said correction data storing means from which to read said correction data in accordance with clock pulses obtained by multiplying frequencies of synchronization signals; and central processing means for computing said correction data, and writing said data to said correction data storing means at addresses corresponding to locations on said picture, said central processing means including: (a) means for computing said correction data by using a correcting function which includes a coefficient that is variably set and a variable indicating a deflection scanning position when adjusting the convergence, (b) time division means for splitting one horizontal scanning period into a plurality of access periods, each shorter than said horizontal scanning period, said plurality of access periods corresponding to a number of said sampling points arranged in a horizontal direction of said picture scanning, and (c) means for dividing said access periods into a first period which is a time required to addressing by said readout address generating means, and a second access period of said central processing means to said correction data storing means.

Claim 19

A circuit as in claim 15 further comprising a first buffer connected between said central processing means and said correcting data storing means, and a second buffer connected between said readout address generating means and said correction data storing means, said first and second buffers being controlled by said time division means such that said first buffer is enabled during said first period and said second buffer is enabled during said second period.

Claim 20

A digital convergence circuit as in claim 16 wherein said synchronization signals are horizontal synchronization signals.

Claim 21

A circuit as in claim 17 further comprising clock pulse generating means for multiplying frequencies of said horizontal synchronization signals of said picture to produce said clock pulses.

Claim 22

An apparatus as in claim 16 further comprising means for dividing the picture into a plurality of sections.

Claim 23

A circuit as in claim 19 wherein said dividing means includes timing generating means for producing a timing pulse at periods of a horizontal scanning period divided by said predetermined section.

Claim 24

A digital convergence circuit comprising: correction data storing means for storing correction data at respective addresses to correct a convergence deviation of a scanning line of a picture, said correction data storing means storing data for each of a plurality of sampling points of said correction data storing means which split said picture into a matrix; readout address generating means, connected to address said correcting data storing means, for designating an address of said correction data storing means from which to read said correction data in accordance with clock pulses obtained by multiplying frequencies of horizontal synchronization signals; central processing means for computing said correction data, and for writing said data to said correction data storing means at addresses corresponding to locations on said picture, said central processing means including means for computing said correction data by using a correcting function which includes a coefficient that is variably set, and a variable indicating a deflection scanning position when adjusting the convergence; and timing generating means, for allocating (a) a plurality of short periods into which one horizontal scanning period is split in proportion to the number of sampling points arranged in the horizontal direction, and (b) a period left in each short period after an access period to said correction data storing means by said central processing means as an addressing period, said addressing period being defined as a fixed period which does not fluctuate with a horizontal deflection frequency.

Claim 25

A digital convergence circuit comprising: correction data storing means for storing correction data at respective addresses to correct a convergence deviation of a scanning line of a picture, said correction data storing means storing data for each of a plurality of sampling points of said correction data storing means which split said picture into a matrix; readout address generating means, connected to address said correcting data storing means, for designating an address of said correction data storing means from which to read said correction data in accordance with clock pulses obtained by multiplying frequencies of horizontal synchronization signals; central processing means for computing said correction data, and for writing said data to said correction data storing means at addresses corresponding to locations on said picture, said central processing means including means for computing said correction data by using a correcting function which includes a coefficient that is variably set, and a variable indicating a deflection scanning position when adjusting the convergence; and timing generating means, for allocating (a) a plurality of short periods into which one horizontal scanning period is split in proportion to the number of sampling points arranged in the horizontal direction, and (b) a period left in each short period after an access period to said correction data storing means by said central processing means as an addressing period, said addressing period being defined as a fixed period which does not fluctuate with a horizontal deflection frequency.

Claim 26

A circuit as in claim 21 wherein said timing generating means includes a monostable multivibrator for producing a pulse with a fixed time period that defines said fixed period.

Claim 27

A circuit as in claim 22 further comprising a first buffer connected between said central processing means and said correcting data storing means, and a second buffer connected between said readout address generating means and said correction data storing means, said first and second buffers being controlled by said timing generating means such that said first buffer is enabled during said first period and said second buffer is enabled during said second period.

Claim 28

A circuit as in claim 21, further comprising a first buffer connected between said central processing means and said correcting data storing means, and a second buffer connected between said readout address generating means and said correction data storing means, said first and second buffers being controlled by said timing generating means such that said first buffer is enabled during said first period and said second buffer is enabled during said second period.

Claim 29

A circuit as in claim 23 further comprising clock pulse generating means for multiplying frequencies of said horizontal synchronization signals of said picture to produce said clock pulses.

Claim 30

An apparatus as in claim 23 further comprising means for dividing the picture into a plurality of sections.

Claim 31

A circuit as in claim 26 wherein said dividing means includes timing generating means for producing a timing pulse at periods of a horizontal scanning period divided by said predetermined section.

Claim 34

A method as in claim 28 wherein said fundamental correction waves include parabolic undulation waves, serrated undulation waves, parabolic undulation waves amplitude-modulated by serrated undulation waves and serrated undulation waves amplitude-modulated by parabolic undulation waves.

Claim 35

A method as in claim 28 comprising the further step of controlling a readout starting address in accordance with a number of scanning lines of the picture, so that a same correction data is obtained at a center of the picture scan independent of the number of scanning lines.

Claim 36

A method as in claim 28 comprising the further steps of splitting one horizontal scanning period into a plurality of access periods, each shorter than said horizontal scanning period, said plurality of access periods corresponding to a number of sampling points arranged in a horizontal direction of said picture scanning; dividing said access periods into a first period which is a time required for addressing by a readout generating structure and a second period which is an access period by said central processing structure; and controlling said readout generating and central processing structures such that they operate only during their respective access periods.

Claim 37

A method as in claim 31 wherein said addressing period is a fixed period which does not fluctuate with horizontal deflection frequency.