Skew compensated RS422 buffer

Claim 2

A skew compensated buffer for providing complementary skew compensated buffer output signals in response to buffer input signals, including: output driver means for receiving complementary compensated drive signals and providing complementary buffer output signals in response thereto, the output driver means characterized by asymmetric switching characteristics whereby buffer output signals in response to drive signals of a first transition are delayed by an inherent skew period with respect to buffer output signals in response to drive signals of a second transition; and skew compensation means for receiving buffer input signals and providing the complementary compensated drive signals in response thereto, the skew compensation means including unclocked means for delaying drive signals of a second transition in response to switching of the buffer input signals by a delay period substantially equal to the inherent skew period, to produce the compensated drive signals and compensate for the asymmetric switching characteristics of the output driver means.

Claim 3

The skew compensated buffer of claim 1 wherein the skew compensation means includes: NOR gate means having a first input terminal connected to receive the buffer input signals, a second input terminal and an output terminal, for providing a first of the complementary compensated drive signals as a logical NOR function of the signals received at its first and second input terminals; AND gate means having a first input terminal connected to receive the buffer input signals, a second input terminal and an output terminal, for providing a second of the complementary compensated drive signals as a logical AND function of the signals received at its first and second input terminals; first delay gate means for propagating the buffer input signals to the second input terminal of the NOR gate means, and for delaying signals propagated to the second input terminal of the NOR gate means by a delay period substantially equal to the inherent skew period of the output driver means; and second delay gate means for propagating the buffer input signals to the second input terminal of the AND gate means, and for delaying signals propagated to the second input terminal of the AND gate means by a delay period substantially equal to the inherent skew period of the output driver means.

Claim 4

The skew compensated buffer of claim 2 wherein: the first delay gate means includes one or more OR gates connected in series with the second input terminal of the AND gate means; and the second delay gate means includes one or more OR gates connected in series with the second input terminal of the AND gate means.

Claim 5

The skew compensated buffer of claim 2 wherein the skew compensation means further includes: first level shifter means coupled between the first delay gate means and the second input terminal of the NOR gate means, for level shifting the signals applied to the second input terminal of the NOR gate means from the first delay gate means; second level shifter means for level shifting the buffer input signals propagates to the first terminals of the NOR gate means and the AND gate means; and third level shifter means coupled between the second delay gate means and the AND gate means, for level shifting the signals coupled to the second input terminal of the AND gate means from the second delay gate means.

Claim 6

The skew compensated buffer of claim 1 and further including a pair of level shifter means coupled between the skew compensation means and the output driver means for level shifting the complementary compensated drive signals coupled to the output driver means.

Claim 7

The skew compensated buffer of claim 5 wherein: the skew compensation means is fabricated of CML logic; the output driver means is fabricated of TTL logic; and the level shifter means includes CML-to-TTL level shifters.

Claim 8

A skew compensated interface buffer for providing complementary skew compensated buffer output signals in response to buffer input signals, including: output driver means for receiving complementary compensated drive signals and for providing complementary buffer output signals in response thereto, the output driver means characterized by asymmetric switching characteristics whereby buffer output signals in response to drive signals of a first transition are delayed by an inherent skew period with respect to buffer output signals in response to drive signals of a second transition; NOR gate means having a first input terminal connected to receive the buffer input signals, a second input terminal and an output terminal, for providing a first of the complementary compensated drive signals as a logical NOR function of the signals received at its first and second input terminals; AND gate means having a first input terminal connected to receive the buffer input signals, a second input terminal and an output terminal, for providing a second of the complementary compensated drive signals as a logical AND function of the signals received at its first and second input terminals; first unclocked delay gate means for propagating the buffer input signals to the second input terminal of the NOR gate means, and for delaying the signals propagated to the second input terminal of the NOR gate means by a delay period substantially equal to the inherent skew period of the output driver means; and second delay gate means for propagating the buffer input signals to the second input terminal of the AND gate means, and for delaying the signals propagated to the second input terminal of the AND gate means by a delay period substantially equal to the inherent skew period of the output driver means.

Claim 9

A skew compensated interface buffer for providing complementary skew compensated buffer output signals in response to buffer input signals, including: output driver means for receiving complementary compensated drive signals and for providing complementary buffer output signals in response thereto, the output driver means characterized by asymmetric switching characteristics whereby buffer output signals in response to drive signals of a first transition are delayed by an inherent skew period with respect to buffer output signals in response to drive signals of a second transition; NOR gate means having a first input terminal connected to receive the buffer input signals, a second input terminal and an output terminal, for providing a first of the complementary compensated drive signals as a logical NOR function of the signals received at its first and second input terminals; AND gate means having a first input terminal connected to receive the buffer input signals, a second input terminal and an output terminal, for providing a second of the complementary compensated drive signals as a logical AND function of the signals received at its first and second input terminals; first unclocked delay gate means for propagating the buffer input signals to the second input terminal of the NOR gate means, and for delaying the signals propagated to the second input terminal of the NOR gate means by a delay period substantially equal to the inherent skew period of the output driver means; and second delay gate means for propagating the buffer input signals to the second input terminal of the AND gate means, and for delaying the signals propagated to the second input terminal of the AND gate means by a delay period substantially equal to the inherent skew period of the output driver means.

Claim 10

The skew compensated buffer of claim 7 wherein: the NOR gate means, AND gate means, first delay gate means and second gate delay means are formed of CML logic; the output driver means is formed of TTL logic; and the buffer further includes a pair of CML-to-TTL level shifters coupling the complementary compensated drive signals to the output driver means.

Claim 11

The skew compensated buffer of claim 8 and further including: a first level shifter propagating the buffer input signals to the first input terminals of the AND gate means and the NOR gate means; a second level shifter coupling the first delay gate means to the second input terminal of the NOR gate means; and a third level shifter coupling the second delay gate means to the second input terminal of the AND gate means.

Claim 12

The skew compensated buffer of claim 9 and further including: a fourth level shifter coupling the output terminal of the NOR gate means to a first of the CML-to-TTL level shifters; and a fifth level shifter coupling the output terminal of the AND gate means to a second of the CML-to-TTL level shifters.