US4866719A
Expired / Lapsed
US
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System and method for performing error correction on still frame audio tape format video signals
Assignee: Sony Corp
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Filing: 1988-03-21
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Granted: 1989-09-12
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Expires: 2008-03-21
Abstract
Abstract A system and method for performing error correction on an SFAT format video signal which has been encoded using an error correction code ECC2, and generating a video signal reconstructed from the error-corrected input signal. The error code preferably is a cross interleave Reed-Solomon code. In a preferred embodiment, the system is capable of reconstructing the output video signal so that it has either SFA or SFAT format. Since an SFAT signal includes duobinary encoded data in its active video areas, and thus may be doubly error encoded using two error correction codes (ECC1 and ECC2), the invention is capable of generating from such a doubly encoded signal an ECC1 error-encoded video signal, in SFA (or SFAT) format, which has been error-corrected using error code ECC2. This capability is particularly advantageous where the invention is embodied in a video disk mastering system or method. In a preferred embodiment, the invention also determines the error rate of the input signal and generates a report signal indicative of the input signal's detected error rate. A preferred embodiment of the invention performs both error correction and error detection on-line, in real time, and automatically.
Inventors
- 👤 Donald E. Morgan
- 👤 Michael B. Shields
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:10
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/80; H04N9/82; H04N9/8205; H04N9/8211; H04N9/8216; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; H04N1/00; H04N1/32; H04N1/32101; H04N1/32106; H04N1/32117; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N5/926; H04N5/9265; H04N5/93; H04N5/94; H04N5/945; H04N9/802; H04N2201/00; H04N2201/32; H04N2201/3201; H04N2201/3261; H04N2201/3264
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
157 words
A system for performing error correction on an SFAT format video signal having error encoded duobinary digital data in at least one of its active video areas, including: (a) a data memory unit; (b) means for extracting the duobinary digital data from the SFAT video signal; (c) means for receiving the extracted duobinary digital data from element (b), converting the extracted duobinary digital data into parallel digital data, and storing the parallel digital data in the memory unit; (d) an error correction unit coupled to the memory unit for receiving digital data stored in the memory unit, performing error correction on the received digital data, and returning the error corrected data to the memory unit; and (e) video signal generating means for receiving the error corrected data from the memory unit, and generating from the error corrected data an error corrected video signal having the error corrected data in at least one of its active video areas.
Claim 2
Independent Claim
157 words
A system for performing error correction on an SFAT format video signal having error encoded duobinary digital data in at least one of its active video areas, including: (a) a data memory unit; (b) means for extracting the duobinary digital data from the SFAT video signal; (c) means for receiving the extracted duobinary digital data from element (b), converting the extracted duobinary digital data into parallel digital data, and storing the parallel digital data in the memory unit; (d) an error correction unit coupled to the memory unit for receiving digital data stored in the memory unit, performing error correction on the received digital data, and returning the error corrected data to the memory unit; and (e) video signal generating means for receiving the error corrected data from the memory unit, and generating from the error corrected data an error corrected video signal having the error corrected data in at least one of its active video areas.
Claim 3
Dependent Claim
16 words
The system of claim 1, wherein the duobinary digital data is a duobinary digitized audio signal.
Claim 4
Dependent Claim
42 words
The system of claim 1, wherein the duobinary digital data is doubly error encoded using two error correction codes (ECC1 and ECC2), and the error correction unit employs the ECC2 error code to correct the digital data received from the memory unit.
Claim 5
Dependent Claim
72 words
The system of claim 3, wherein the error corrected video signal generating means is capable of operating in a first mode in which it generates an SFAT format video signal having the error corrected data in at least one of its active video areas, and in a second mode in which it generates an SFA format video signal having the error corrected data in at least one of its active video areas.
Claim 6
Dependent Claim
16 words
The system of claim 4, wherein the ECC2 error code is a cross interleave Reed-Solomon code.
Claim 7
Dependent Claim
36 words
The system of claim 1, wherein the error corrected video signal generating means is capable of generating an SFAT format video signal having the error corrected data in at least one of its active video areas.
Claim 8
Dependent Claim
36 words
The system of claim 1, wherein the error corrected video signal generating means is capable of generating an SFA format video signal having the error corrected data in at least one of its active video areas.
Claim 9
Dependent Claim
72 words
The system of claim 1, wherein the error corrected video signal generating means is capable of operating in a first mode in which it generates an SFAT format video signal having the error corrected data in at least one of its active video areas, and in a second mode in which it generates an SFA format video signal having the error corrected data in at least one of its active video areas.
Claim 10
Dependent Claim
60 words
The system of claim 1, also including: (f) means for generating a clock signal and supplying the clock signal to element (c), wherein the SFAT video signal includes a synchronization signal identifying the start of each line including said error encoded duobinary digital data, and wherein element (c) includes means for synchronizing the clock signal with each said synchronization pulse.
Claim 11
Dependent Claim
70 words
The system of claim 9, also including: (g) means for generating address signals from the synchronized clock signal, each said address signal identifying a portion of the parallel digital data; and (h) means for generating header signals from the address signals; and wherein element (e) includes means for combining the header signals with the error corrected data read out from the memory unit to generate said error corrected video signal.
Claim 12
Dependent Claim
31 words
The system of claim 1, also including: (i) means for determining the error rate of the SFAT format video signal and generating a report signal indicative of the detected error rate.
Claim 13
Independent Claim
133 words
A method for performing error correction on an SFAT format video signal having error encoded duobinary digital data in at least one of its active video areas, including the steps of: (a) extracting the duobinary digital data from the SFAT format video signal; (b) converting the extracted duobinary digital data into parallel digital data, and storing the parallel digital data in a memory unit; (c) reading out digital data stored in the memory unit during step (b), performing error correction on the digital data read out from the memory unit, and returning the error corrected data to the memory unit; and (d) reading out the error corrected data from the memory unit and generating an error corrected video signal having said error corrected data in at least one of its active video areas.
Claim 14
Independent Claim
133 words
A method for performing error correction on an SFAT format video signal having error encoded duobinary digital data in at least one of its active video areas, including the steps of: (a) extracting the duobinary digital data from the SFAT format video signal; (b) converting the extracted duobinary digital data into parallel digital data, and storing the parallel digital data in a memory unit; (c) reading out digital data stored in the memory unit during step (b), performing error correction on the digital data read out from the memory unit, and returning the error corrected data to the memory unit; and (d) reading out the error corrected data from the memory unit and generating an error corrected video signal having said error corrected data in at least one of its active video areas.
Claim 15
Dependent Claim
33 words
The method of claim 13, also including the steps of: (e) determining the error rate of the SFAT format video signal; and (f) generating a report signal indicative of the detected error rate.
Claim 16
Dependent Claim
101 words
The method of claim 13, wherein the SFAT video signal includes a synchronization signal identifying the start of each line including said error encoded duobinary digital data, also including the steps of: (g) generating a clock signal, synchronizing the clock signal with each said synchronization pulse, and employing the synchronized clock signal to generate address signals each identifying a portion of the parallel digital data; and (h) employing the address signals to generate header signals, and combining the header signals with the error corrected data read out from the memory unit in step (d) to generate said error corrected video signal.
Claim 17
Dependent Claim
17 words
The method of claim 13, wherein the duobinary digital data is a duobinary encoded digitized audio signal.
Claim 18
Dependent Claim
33 words
The method of claim 13, wherein the duobinary digital data is doubly error encoded using two error correction codes (ECC1 and ECC2), and the ECC2 error code is employed in performing step (c).
Claim 19
Dependent Claim
58 words
The method of claim 16, wherein the error correction code ECC2 is a cross interleave Reed-Solomon code including an outer code layer C1 and an inner code layer C2, wherein the digital data stored in the memory unit is organized into blocks of data, and wherein step (c) includes four error correction passes on each block of data.
Claim 20
Dependent Claim
47 words
The method of claim 16, wherein the first of the four passes employs the C1 code, the second of the four passes employs the C2 code, the third of the four passes employs the C1 code, and the fourth of the four passes employs the C2 code.
Claim 21
Dependent Claim
15 words
The method of claim 16, in which the error corrected video signal has SFAT format.
Claim 22
Dependent Claim
15 words
The method of claim 16, in which the error corrected video signal has SFA format.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-11 | 1993-03-13 | 1993-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-11 | 1997-03-13 | 1997-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-11 | 2001-03-13 | 2001-09-12 | $7700.00 | Window Closed / Lapsed |