← Back to Patent Explorer
US4860121A Expired / Lapsed US ⏱️ 0.0 years remaining

Detector circuit for detecting drop-out in reproduced digital data

Assignee: Pioneer Corp
•
Filing: 1988-03-18
•
Granted: 1989-08-22
•
Expires: 2008-03-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A drop-out detector circuit for use in a data reproducing device in which a reproduced high-frequency signal is digitized. The most significant bit of the digitized signal is sampled, and its logic state detected over a predetermined number of sampling periods. Both high- and low-frequency drop-outs can be detected from the detected logic state pattern of the most significant bit.

Inventors

  • 👤 Toshio Gotoh

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 20:16
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/88; H04N9/882; H04N9/885

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 115 words
A drop-out detector circuit for a device for reproducing sequentially recorded digital data from a signal recorded on a recording medium, the recorded signal comprising a high-frequency modulated signal, comprising: means for reading said signal recorded on said recording medium and producing a digitized signal therefrom; means for extracting from each of a plurality of sequential data values contained within said digitized signal at least one bit indicative of a polarity of the respective data value; and means for detecting when a sequence of a predetermined number of the bits extracted from a plurality of said sequential data values is in a predetermined bit pattern, an output of said detecting means forming a drop-out signal.
Claim 2
Dependent Claim 115 words
A drop-out detector circuit for a device for reproducing sequentially recorded digital data from a signal recorded on a recording medium, the recorded signal comprising a high-frequency modulated signal, comprising: means for reading said signal recorded on said recording medium and producing a digitized signal therefrom; means for extracting from each of a plurality of sequential data values contained within said digitized signal at least one bit indicative of a polarity of the respective data value; and means for detecting when a sequence of a predetermined number of the bits extracted from a plurality of said sequential data values is in a predetermined bit pattern, an output of said detecting means forming a drop-out signal.
Claim 3
Dependent Claim 24 words
The drop-out detector circuit of claim 1, wherein said predetermined bit pattern comprises a plurality of data bits all in the same logic state.
Claim 4
Dependent Claim 51 words
The drop-out detector circuit of claim 1, wherein said detecting means comprises: means for storing a standard data bit pattern; and means for comparing said sequence of a predetermined number of said at least one bits extracted from a plurality of said sequential data values with said standard data bit pattern.
Claim 5
Dependent Claim 20 words
The drop-out detector circuit of claim 1, wherein said at least one bit comprises at least one most significant bit.
Claim 6
Dependent Claim 129 words
A drop-out detector circuit for a device for reproducing sequentially recorded digital data from a signal recorded on a recording medium, the recorded signal including a high-frequency modulated signal, comprising: means for reading said signal recorded on said recording medium and producing a digitized signal therefrom; means for delaying said digitized signal by a period equivalent to a period of one digital value contained therein; means for subtracting from an output of said delaying means a present digital value contained in said digitized signal; means for storing most significant bits of a predetermined number of sequential output values of said subtracting means; and means for detecting when a sequence of a predetermined number of said most significant bits stored by said storing means is in a predetermined bit pattern.
Claim 7
Dependent Claim 129 words
A drop-out detector circuit for a device for reproducing sequentially recorded digital data from a signal recorded on a recording medium, the recorded signal including a high-frequency modulated signal, comprising: means for reading said signal recorded on said recording medium and producing a digitized signal therefrom; means for delaying said digitized signal by a period equivalent to a period of one digital value contained therein; means for subtracting from an output of said delaying means a present digital value contained in said digitized signal; means for storing most significant bits of a predetermined number of sequential output values of said subtracting means; and means for detecting when a sequence of a predetermined number of said most significant bits stored by said storing means is in a predetermined bit pattern.
Claim 8
Dependent Claim 24 words
The drop-out detector circuit of claim 5, wherein said predetermined bit pattern is a set of data bits all in the same logic state.

References Cited (Backward Citations)

US4498104A Cited
US4591925A Cited
US4760470A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-08-21 1993-02-20 1993-08-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-08-21 1997-02-20 1997-08-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-08-21 2001-02-20 2001-08-22 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag