Digital circuit arrangement for quantization-noise reduction

Claim 2

A digital circuit arrangement comprising an interpolation filter (1) for oversampling a digital input signal which appears as a sequence of discrete-amplitude samples with a specific sampling rate, and a noise shaper (2) comprising a quantizer, means responsive to the input and output of said quantizer for performing a quantization-error signal, an adder stage (3) whose output is coupled to the input of said quantizer (7), having a first input coupled to the output of said interpolation filter (1) and a second input, and a limiter (10) in cascade with each other coupled between the output of said quantization-error signal forming means and said second input of the adder stage for limiting and filtering the quantization-error signal.

Claim 3

A digital circuit arrangement as claimed in claim 1, characterized in that the arrangement comprises a subtractor (6) for generating the quantization-error signal, which subtractor has its first input coupled to the output of the adder stage (3), its second input coupled to the output of the quantizer (7), and its output coupled to an input of the limiter (10), whose output is coupled to an input of the filter arrangement (4), which has its output coupled to the second input of the adder stage (3).

Claim 4

A digital circuit arrangement as claimed in claim 2, characterized in that the filter arrangement (4) comprises a first register (12) whose input is coupled to the limiter (10) and whose output is coupled to an amplifier (13) and to a second register (14), and in that the filter arrangement (4) comprises a further subtractor (16) whose first input is coupled to the second register (14), whose second input is coupled to the amplifier (13) and whose output is coupled to the output of the filter arrangement (4).

Claim 5

A digital circuit arrangement as claimed in any one of the preceding claims, characterized in that the quantizer (7) comprises means for generating at its output a 1-bit signal which assumes a first state if the output signal of the adder stage (3) is positive and which assumes a second state if the output signal of the adder stage (3) is negative.

Claim 6

A quantization noise reducing circuit responsive to an input digital signal representing a temporal sequence of discrete samples, for producing an output signal therefrom, said apparatus comprising: an interpolation filter for oversampling said input digital signal; a port for said output signal; a noise shaper interposed between the output of the interpolation filter and said port comprising: a quantizer having an output coupled to said port; a first signal path coupling the output of said interpolation filter to the input of said quantizer; means responsive to the input and output of said quantizer for forming a quantization-error signal; a second signal path including means for sequentially operating on said quantization-error signal and coupling the result of said sequentially operation to the input of said quantizer, said means for sequentially operating on said quantization-error signal comprising a filter arrangement and a limiter.

Claim 7

A quantization noise reducing circuit responsive to an input digital signal representing a temporal sequence of discrete samples, for producing an output signal therefrom, said apparatus comprising: an interpolation filter for oversampling said input digital signal; a port for said output signal; a noise shaper interposed between the output of the interpolation filter and said port comprising: a quantizer having an output coupled to said port; a first signal path coupling the output of said interpolation filter to the input of said quantizer; means responsive to the input and output of said quantizer for forming a quantization-error signal; a second signal path including means for sequentially operating on said quantization-error signal and coupling the result of said sequentially operation to the input of said quantizer, said means for sequentially operating on said quantization-error signal comprising a filter arrangement and a limiter.

Claim 8

The circuit of claim 5 wherein said limiter feeds said filter arrangement.

Claim 9

The circuit of claim 5 wherein said filter arrangement comprises a second-order filter.

Claim 10

The circuit of claim 5 wherein said filter arrangement comprises a first register fed by the output of said limiter, a second register fed by the output of said first register and means arithmetically combining the outputs of said first and second registers.

Claim 11

The circuit of claim 5 wherein the output from said noise shaper has a digital word length less than the digital word length at the output of the filter arrangement.

Claim 12

The circuit of claim 5 further comprising an analog to digital converter fed by the output of said quantizer and feeding said output port.

Claim 13

The circuit of claim 9 wherein the output from said noise shaper has a digital word length of only one bit.

Claim 14

The circuit of claim 9 wherein the input digital signal is of a digital word length less than the digital word length at the output of said filter arrangement.