Complex waveform multiplexer for liquid crystal displays

Claim 2

A liquid crystal display comprising: a matrix display panel having a two-dimensional array of liquid crystal display elements switchable between at least two display states; at least one of a row and a column driver circuit means, each driver circuit means having at least two drive level inputs, a logical selection input, and a plurality of outputs connected to control lines of the display elements for switching the display elements between said display states; display controller means connected to the logical selection input for connecting the display to a graphical data source for controlling selection of display states of the display elements, said controller means having a timing signal output controllably coupled to the driver circuit means: waveform generator means having at least two outputs, each output being connected to one of the drive level inputs for applying a time variant signal to the driver circuit means, said waveform generator means further having timing and switching means and generating at least two predetermined waveforms for each driver circuit which vary among at least three levels within a predetermined dynamic range and through at least three phases in a predetermined sequence for each occurrence of the logical selection of the display state of the display elements, and providing each of said waveforms as said time variant signals to the drive level inputs, said timing and switching means including at least one phase timing signal input; phase timing means having an output coupled to the phase timing signal input and responsive to the controller means timing signal to provide phase timing signals to the timing and switching means for synchronizing the waveforms to a predetermined phase with the logical selection of the display elements.

Claim 3

A display according to claim 1 in which the waveform generator means includes at least two output buffer means, each having one of the waveform output signals as an input, for inputting each of said waveforms to a different drive level input.

Claim 4

A display according to claim 2 in which the output buffer means are arranged to provide a gain and output level within a predetermined dynamic range sufficient to enable the column driver circuit means to actuate the display elements for switching between said two states.

Claim 5

A display according to claim 2 in which the output buffer means are arranged to provide a gain and offset drive level for the time variant drive signals such that the conditions V SSH ≦V4≦V1≦V DD for the row drivers and V SSH ≦V3≦V2≦V DD for the column drivers are always satisfied, where V SSH , V4, V3, V2 and V1 are variables defining said predetermined waveforms and V DD is a reference voltage.

Claim 6

A display according to claim 2 in which the output buffer means each have a low impedance output.

Claim 7

A display according to claim 2 in which the timing and switching means is operative to switch at least one of the waveform output signals among three and only three predetermined levels and through three and only three phases.

Claim 8

A display according to claim 1 in which the matrix display panel is a ferroelectric liquid crystal display and the waveform generator means includes switching means for switching among three and only three predetermined levels and through three and only three phases to generate a waveform output signal defining said time variant signal.

Claim 9

A display according to claim 7 in which the controller means includes timing means for generating a timing signal output to the driver circuit means for controllng the logical selection of the display states of the display elements and the waveform generator means includes phase timing means responsive to the timing signal output for synchronizing the waveform output signal to a predetermined phase with the logical selection of the display elements.

Claim 10

A display according to claim 1 wherein said controller means includes means for generating a first logical selection signal comprising a data signal which is provided to a first logical selection input; said driver circuit means includes a second logical selection input; and said phase timing means further includes means responsive to the controller means timing signal for producing a second logical selection signal on an output thereof which is connected to said second logical selection input, said second logical selection signal having a predetermined phase relationship with the waveforms applied to the drive level inputs for switching the driver circuit means outputs.

Claim 11

A display according to claim 9 wherein: the controller means timing signal comprises horizontal synchronization pulses; said phase timing means includes means for creating an integer number of phase transitions defining at least three phases for each horizontal synch pulse period, said waveform generator means being responsive to produce said predetermined waveforms with phase changes in synchrony with said phase transitions; and said means for producing a second logical selection signal includes means for switching said second signal at least once in synchrony with one of the phase transitions during each horizontal synchronization pulse period.

Claim 12

A display according to claim 1 wherein the controller means timing signal comprises a horizontal synchronization pulse.

Claim 13

A circuit for complex waveform multiplexing of a matrix display panel having a two-dimensional array of liquid crystal display elements switchable between at least two display states, the circuit comprising: row and column driver circuit means, each driver circuit means having at least two drive level inputs, a logical selection input, and a plurality of outputs connected to control lines of the display elements for switching the display elements between said states; display controller means controllably connected to the logical selection input for connecting the display to a graphical data source to control selection of display states of the display elements; and waveform generator means having at least two outputs, each output being connected to one of the drive level inputs for applying a time variant output signal to the driver circuit means; the waveform generator means including a timing and switching means for generating, as each time variant output signal, a predetermined waveform which varies among three and only three levels with a predetermined dynamic range and through three and only three phases in a predetermined sequence for each occurrence of the logical selection of the display state of the display elements, said timing and switching means having an input connected to receive a timing signal from the controller means and phase timing means responsive to the timing signal for synchronizing the three-level, three-phase waveforms to a predetermined phase with the logical selection of the display elements.

Claim 14

A circuit for complex waveform multiplexing of a matrix display panel having a two-dimensional array of liquid crystal display elements switchable between at least two display states, the circuit comprising: row and column driver circuit means, each driver circuit means having at least two drive level inputs, a logical selection input, and a plurality of outputs connected to control lines of the display elements for switching the display elements between said states; display controller means controllably connected to the logical selection input for connecting the display to a graphical data source to control selection of display states of the display elements; and waveform generator means having at least two outputs, each output being connected to one of the drive level inputs for applying a time variant output signal to the driver circuit means; the waveform generator means including a timing and switching means for generating, as each time variant output signal, a predetermined waveform which varies among three and only three levels with a predetermined dynamic range and through three and only three phases in a predetermined sequence for each occurrence of the logical selection of the display state of the display elements, said timing and switching means having an input connected to receive a timing signal from the controller means and phase timing means responsive to the timing signal for synchronizing the three-level, three-phase waveforms to a predetermined phase with the logical selection of the display elements.

Claim 15

A circuit according to claim 12 in which the controller means includes means for generating a timing signal output to the driver circuit means for synchronizing the logical selection of the display elements.

Claim 18

A method according to claim 14 including: generating a timing signal from the graphical data source; applying the timing signal to the logical control means for timing the selection among the drive level inputs; and synchronizing the waveforms to a predetermined phase with the logical selection of the display elements in accordance with the timing signal.

Claim 19

A method according to claim 14 wherein the switching step is controlled so that the predetermined waveforms for each driver circuit vary among three and only three levels within a predetermined dynamic range and through three and only three phases in a predetermined sequence for each occurrence of the logical selection of the display state of the display elements.

Claim 20

A liquid crystal display comprising: a matrix display panel having a two-dimensional array of liquid crystal display elements switchable between at least two display states; at least one of a row and a column driver circuit means, each driver circuit means having at least two drive level inputs, at least two logical selection inputs, and a plurality of outputs connected to control lines of the display elements for switching the display elements between said display states; display controller means connected to the logical selection inputs for connecting the display to a graphical data source for controlling selection of display states of the display elements, and including timing means for generating a timing signal output to the driver circuit means for synchronizing the logical selection of the display elements; and; and waveform generator means having at least two outputs, each output being connected to one of the drive level inputs for applying a time variant signal to the driver circuit means, said waveform generator means further having: timing and switching means for generating at least two predetermined waveforms for each driver circuit which vary among at least three levels within a predetermined dynamic range and through at least three phases in a predetermined sequence for each occurrence of the logical selection of the display state of the display elements, and providing each of said predetermined waveforms as an output signal, said timing and switching means includes at least one input connected to receive the timing signal from the controller means and phase timing means responsive to the timing signal for synchronizing the waveform to a predetermined phase with the logical selection of the display elements; and; at least two output buffer means, each having one of said waveform output signals as an input, for inputting each of said waveforms to a different drive level input, said output buffer means being arranged to provide a gain and offset drive level for the time variant drive signals such that one time variant signal is always less than or equal to another.

Claim 21

A liquid crystal display comprising: a matrix display panel having a two-dimensional array of liquid crystal display elements switchable between at least two display states; at least one of a row and a column driver circuit means, each driver circuit means having at least two drive level inputs, at least two logical selection inputs, and a plurality of outputs connected to control lines of the display elements for switching the display elements between said display states; display controller means connected to the logical selection inputs for connecting the display to a graphical data source for controlling selection of display states of the display elements, and including timing means for generating a timing signal output to the driver circuit means for synchronizing the logical selection of the display elements; and; and waveform generator means having at least two outputs, each output being connected to one of the drive level inputs for applying a time variant signal to the driver circuit means, said waveform generator means further having: timing and switching means for generating at least two predetermined waveforms for each driver circuit which vary among at least three levels within a predetermined dynamic range and through at least three phases in a predetermined sequence for each occurrence of the logical selection of the display state of the display elements, and providing each of said predetermined waveforms as an output signal, said timing and switching means includes at least one input connected to receive the timing signal from the controller means and phase timing means responsive to the timing signal for synchronizing the waveform to a predetermined phase with the logical selection of the display elements; and; at least two output buffer means, each having one of said waveform output signals as an input, for inputting each of said waveforms to a different drive level input, said output buffer means being arranged to provide a gain and offset drive level for the time variant drive signals such that one time variant signal is always less than or equal to another.

Claim 22

A display according to claim 17 wherein said output buffer means is arranged to provide a gain and offset drive level for the time variant drive signal such that the conditions V SSH ≦V4≦V1≦V DD for the row drivers and V SSH ≦V3≦V2≦V DD for the column drivers are satisifed, where V SSH , V4, V3, V2 and V1 are variables defining said predetermined waveform signals and V DD is a reference voltage.

Claim 23

A display according to claim 17 in which the output buffer means are arranged to provide a gain and output level within a predetermined dynamic range sufficient to enable the column driver circuit means to actuate the display elements for switching between said two states.

Claim 24

A display according to claim 17 in which the output buffer means each have a low impedance output.

Claim 25

A display according to claim 17 in which the timing and switching means is operative to switch at least one of the waveform output signals among three and only three predetermined levels and through three and only three phases.

Claim 26

A display according to claim 17 in which the matrix display panel is a ferroelectric liquid crystal display and the waveform generator means includes switching means for switching among three and only three predetermined levels and through three and only three phases to generate a waveform output signal defining said time variant signal.

Claim 27

A display according to claim 22 in which the controller means includes timing means for generatng a timing signal output to the driver circuit means for controlling the logical selection of the display states of the display elements and the waveform generator means includes phase timing means responsive to the timing signal output for synchronizing the waveform output signal to a predetermined phase with the logical selection of the display elements.

Claim 28

A display according to claim 22 in which the controller means includes timing means for generating a timing signal output to the driver circuit means for controlling the logical selection of the display states of the display elements and the waveform generator means includes phase timing means responsive to the timing signal output for varying the waveform output signal among three and only three levels and through three and only three phases in a predetermined sequence for each occurrence of the logical selection of the display state of the display elements.

Claim 29

A display according to claim 22 in which the controller means includes timing means for generating a timing signal output to the driver circuit means for controlling the logical selection of the display states of the display elements and the waveform generator means includes phase timing means responsive to the timing signal output for varying the waveform output signal through three and only three phases and among three and only three levels in a predetermined sequence in synchrony with each occurrence of the logical selection of the display state of the display elements.

Claim 30

A display according to claim 25 wherein said phase timing means includes means for generating phases of equal duration in the waveform output signal.