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US4856076A Expired / Lapsed US ⏱️ 0.0 years remaining

Binary coding circuit for OCR

Assignee: Sumitomo Electric Industries Ltd
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Filing: 1987-07-07
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Granted: 1989-08-08
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Expires: 2007-07-07
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Abstract

Abstract This invention provides a binary coding circuit particularly suited for use in an optical character reader which "reads" characters or symbols using a photoelectric conversion cell. A delay circuit has one input for receiving an output of the photoelectric conversion cell, and at least three separate and distinct delayed outputs providing respective delays that are different from each other. A threshold determining circuit is arranged so that when one of the delayed outputs is selected to be a binary-coding target signal, the threshold determining circuit receives as its inputs a plurality of ones of the delayed outputs including one delayed output having a larger delay time than that of the binary-coding target signal and one delayed output having a smaller delay time than that of the binary-coding target signal, so as to produce a threshold signal at a value which is the greater of the delayed signals. A comparator circuit receives at a first input thereof the binary-coding target signal and receives at a second input thereof the threshold signal. It compares the binary-coding target signal with the threshold signal to thereby produce a binary signal of the appropriate level.

Inventors

  • 👤 Naoki Maeda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 19:10
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10851; G06V; G06V30/00; G06V30/10; G06V30/16; G06V30/162

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 247 words
A binary coding circuit for an optical character reader which identifies characters or symbols using a photoelectric conversion cell, comprising: a delay circuit having one input terminal for receiving an output of said photoelectric conversion cell as an input signal, and at least three separate and distinct output terminals providing respective time-shifted output representations of said input signal, said time-shifted output representations having delays that are different from each other; a threshold determining circuit arranged so that when one of said time-shifted output representations of said input signal is selected to be a binary-coding target signal, said threshold determining circuit receives as its inputs a plurality of said time-shifted output representations including one time-shifted output representation having a larger delay time than that of said binary-coding target signal and one time-shifted output representation having a smaller delay time than that of said binary-coding target signal as threshold determining signals for determining a threshold signal, said threshold signal being determined to be the threshold determining signal of said threshold determining signals, having a maximum absolute value for each point in time; and a comparator circuit, having a first input receiving said binary-coding target signal and a second input receiving said threshold signal, for comparing said binary-coding target signal with said threshold signal to thereby produce a binary signal having a first level if said binary-coding target signal is greater than said threshold signal and a second level if said binary-coding target signal is less than said threshold signal.
Claim 2
Dependent Claim 247 words
A binary coding circuit for an optical character reader which identifies characters or symbols using a photoelectric conversion cell, comprising: a delay circuit having one input terminal for receiving an output of said photoelectric conversion cell as an input signal, and at least three separate and distinct output terminals providing respective time-shifted output representations of said input signal, said time-shifted output representations having delays that are different from each other; a threshold determining circuit arranged so that when one of said time-shifted output representations of said input signal is selected to be a binary-coding target signal, said threshold determining circuit receives as its inputs a plurality of said time-shifted output representations including one time-shifted output representation having a larger delay time than that of said binary-coding target signal and one time-shifted output representation having a smaller delay time than that of said binary-coding target signal as threshold determining signals for determining a threshold signal, said threshold signal being determined to be the threshold determining signal of said threshold determining signals, having a maximum absolute value for each point in time; and a comparator circuit, having a first input receiving said binary-coding target signal and a second input receiving said threshold signal, for comparing said binary-coding target signal with said threshold signal to thereby produce a binary signal having a first level if said binary-coding target signal is greater than said threshold signal and a second level if said binary-coding target signal is less than said threshold signal.
Claim 3
Dependent Claim 53 words
A binary coding circuit according to claim 1, wherein said threshold determining circuit comprises an OR circuit for use when the value of said binary-coding target signal becomes high in the area of characters or symbols so that the threshold determining signal having a maximum absolute value is selected as said threshold signal.
Claim 4
Dependent Claim 34 words
A binary coding circuit according to claim 2, further comprising means for amplifying said binary-coding target signal with an amplification factor larger than said threshold signal and adding thereto a negative offset value (-Δ).
Claim 5
Dependent Claim 53 words
A binary coding circuit according to claim 1, wherein said threshold determining circuit comprises an AND circuit for use when the value of said binary-coding target signal becomes low in the area of characters or symbols so that the threshold determining signal having a minimum absolute value is selected as said threshold signal.
Claim 6
Dependent Claim 34 words
A binary coding circuit according to claim 4, further comprising means for amplifying said binary-coding target signal with an amplification factor larger than said threshold signal and adding thereto a positive offset value (+Δ).

References Cited (Backward Citations)

US3534334A Cited
US3987413A Cited
US4446486A Cited
US4442544A Cited
US4430748A Cited
US4584703A Cited
US4468704A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-08-07 1993-02-06 1993-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-08-07 1997-02-06 1997-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-08-07 2001-02-06 2001-08-08 $7700.00 Window Closed / Lapsed

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