Distributed fet amplifier and bias voltage supply circuit therefor

Claim 2

A distributed FET amplifier comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal, first inductor means interconnecting the gate terminals of the adjacent FET elements, second inductor means interconnecting the drain terminals of the adjacent FET elements, an input terminal connected to supply a microwave to said array, an output terminal to be supplied with an amplified microwave, a first terminating means connected between the drain terminal of the FET element positioned at the left end of said array and the ground, and a second terminating means connected between the gate terminal of the FET positioned at the right end of said array and the ground, characterized in that capacitor means having a capacitance greater than the gate-source capacitance of each of said FET elements and inductance element means for grounding the direct current are connected in parallel to each other between the source terminal of each of said FET elements and the ground.

Claim 3

An amplifier as claimed in claim 1, wherein said inductance element means comprises a distributed constant line.

Claim 4

An amplifier as claimed in claim 1, wherein said capacitor means has a capacitance several times as large as said gate-source capacitance and produces a reactance much smaller than that produced by said inductance element means for grounding the direct current in a used frequency.

Claim 5

An amplifier as claimed in claim 3, wherein said inductance element means comprises a distributed constant line.

Claim 6

An amplifier as claimed in claim 1 or 3, wherein said inductance element comprises a series combination comprising an inductance element and a resistor, said first terminating means is a series combination comprising a resistor and a capacitor connected between the terminal t o which a drain bias is applied and the ground, and said second terminating means is a resistor for grounding the direct current.

Claim 7

An amplifier as claimed in claim 5 wherein said inductance element means comprises distributed constant circuit.

Claim 8

A distributed FET amplifier formed as a monolithic integrated circuit on a semiconductor substrate and including an array of FET elements each having a gate terminal, a drain terminal and a source terminal, first inductor means interconnecting the gate terminals of the adjacent FET elements, second inductor means interconnecting the drain terminals of the adjacent FET elements, resistors each interconnecting the source terminal of each of said FET elements and the ground, and capacitors each connected in parallel to said resistor between said source terminal and the ground, said distributed amplifier comprising: a plurality of metal islands arranged alternately with said FET elements in a nearly straight line, each of said capacitors being formed to connect the source terminal of one of the adjacent FET elements and the metal island positioned between said adjacent FET elements; and slits formed on said metal islands such as to separate adjacently disposed capacitors formed on each of said metal islands; said resistor being connected between said metal islands and the source terminals of said FET elements.

Claim 9

A distributed FET amplifier formed as a monolithic integrated circuit on a semiconductor substrate and including an array of FET elements each having a gate terminal, a drain terminal and a source terminal, first inductor means interconnecting the gate terminals of the adjacent FET elements, second inductor means interconnecting the drain terminals of the adjacent FET elements, resistors each interconnecting the source terminal of each of said FET elements and the ground, and capacitors each connected in parallel to said resistor between said source terminal and the ground, said distributed amplifier comprising: a plurality of metal islands arranged alternately with said FET elements in a nearly straight line, each of said capacitors being formed to connect the source terminal of one of the adjacent FET elements and the metal island positioned between said adjacent FET elements; and slits formed on said metal islands such as to separate adjacently disposed capacitors formed on each of said metal islands; said resistor being connected between said metal islands and the source terminals of said FET elements.

Claim 10

An amplifier as claimed in claim 7, wherein said slits are formed in the direction perpendicular to the direction of said array, the length of the slits is smaller than that of one side of said metal islands perpendicular to the direction of said array, thereby constituting two portions in each of said metal islands.

Claim 11

An amplifier as claimed in claim 8 wherein each of said resistors is connected between one of said two portions and the source terminal of said one of the adjacent FET elements.

Claim 12

An amplifier as claimed in claim 8, wherein each of said resistors comprises a first resistor interconnecting one of said two portions and the source terminal of one of said adjacent FET elements and a second resistor interconnecting the other of said two portions and the source terminal of the other of said adjacent FET elements.

Claim 13

A bias voltage supply circuit for supplying a bias voltage to an electric circuit such as a distributed FET amplifier, said supply circuit comprising: an input terminal connected to a voltage source; an output terminal connected to said electric circuit for supplying a bias voltage thereto: a first distributed constant line means, one end thereof being connected to said input terminal and grounded through a capacitor; a second distributed constant line means, one end thereof being open and the other end thereof being connected to the other end of said first distributed constant line means and to said output terminal: and at least one circuit including a resistor connected between a point on said first distributed constant line means and a point on said second distributed constant line means.

Claim 14

A bias voltage supply circuit for supplying a bias voltage to an electric circuit such as a distributed FET amplifier, said supply circuit comprising: an input terminal connected to a voltage source; an output terminal connected to said electric circuit for supplying a bias voltage thereto: a first distributed constant line means, one end thereof being connected to said input terminal and grounded through a capacitor; a second distributed constant line means, one end thereof being open and the other end thereof being connected to the other end of said first distributed constant line means and to said output terminal: and at least one circuit including a resistor connected between a point on said first distributed constant line means and a point on said second distributed constant line means.

Claim 15

A supply circuit as claimed in claim 11, wherein said first and second distributed constant line means have the same length and wherein said circuits are connected between points on said lines at the same distance from said output terminal.

Claim 16

A supply circuit as claimed in claim 12, wherein said circuit comprises a series combination comprising a resistor and a capacitor.

Claim 17

A supply circuit as claimed in claim 11 wherein said first and second distributed constant line means have different lengths.

Claim 18

A distributed FET amplifier having a pair of travelling-wave FET amplifiers disposed in parallel with each other, each of said travelling-wave FET amplifiers comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal, first reactance circuit means having a predetermined value and interconnecting the gate terminals of the adjacent two FET elements in said array, second reactance circuit means having a predetermined value and interconnecting the drain terminals of the adjacent two FET elements in said array, said distributed FET amplifier being characterized in that T-branch means combines the outputs from said pair of travelling-wave FET amplifiers, and that resistors having a predetermined resistance value interconnect the drain terminals of one travelling-wave FET amplifier and the corresponding drain terminals of the other travelling-wave FET amplifier.

Claim 19

A distributed FET amplifier having a pair of travelling-wave FET amplifiers disposed in parallel with each other, each of said travelling-wave FET amplifiers comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal, first reactance circuit means having a predetermined value and interconnecting the gate terminals of the adjacent two FET elements in said array, second reactance circuit means having a predetermined value and interconnecting the drain terminals of the adjacent two FET elements in said array, said distributed FET amplifier being characterized in that T-branch means combines the outputs from said pair of travelling-wave FET amplifiers, and that resistors having a predetermined resistance value interconnect the drain terminals of one travelling-wave FET amplifier and the corresponding drain terminals of the other travelling-wave FET amplifier.

Claim 20

An amplifier as claimed in claim 15, wherein said resistors are positioned from a quarter wave-length of the respective frequencies within a desired frequency band.

Claim 21

An amplifier as claimed in claim 15 or 16, wherein said first and second reactance circuits comprise distributed constant line.

Claim 22

A distributed FET amplifier comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal, first inductor means interconnecting the gate terminals of the adjacent FET elements, second inductor means interconnecting the drain terminals of the adjacent FET elements, an input terminal connected to supply to supply a microwave to said array, an output terminal to be supplied with an amplified microwave, a first terminating means connected between the drain terminal of the FET element positioned at the left end of said array and the ground, and a second terminating means connected between the gate terminal of the FET positioned at the right end of said array and the ground, characterized in that capacitor means having a capacitance greater than the gate source capacitance of each of said FET elements and a series combination of inductance element means and resistor means are connected in parallel to each other between the source terminal of each of said FET elements and the ground, and that said first terminating means is a series combination comprising resistor means and capacitor means connected between the terminal to which a drain bias is applied and the ground, said second terminating means being resistor means for grounding the direct current.

Claim 23

A distributed FET amplifier comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal, first inductor means interconnecting the gate terminals of the adjacent FET elements, second inductor means interconnecting the drain terminals of the adjacent FET elements, an input terminal connected to supply to supply a microwave to said array, an output terminal to be supplied with an amplified microwave, a first terminating means connected between the drain terminal of the FET element positioned at the left end of said array and the ground, and a second terminating means connected between the gate terminal of the FET positioned at the right end of said array and the ground, characterized in that capacitor means having a capacitance greater than the gate source capacitance of each of said FET elements and a series combination of inductance element means and resistor means are connected in parallel to each other between the source terminal of each of said FET elements and the ground, and that said first terminating means is a series combination comprising resistor means and capacitor means connected between the terminal to which a drain bias is applied and the ground, said second terminating means being resistor means for grounding the direct current.

Claim 24

An amplifier as claimed in claim 18, wherein said inductance element means is a distributed constant line.

Claim 25

A distributed FEET amplifier formed as a monolithic integrated circuit on a semiconductor substrate, comprising: an array of FET elements each having a gate terminal, a drain terminal and a source terminal having two sections; first inductor means interconnecting the gate terminals of the adjacent FET elements; second inductor means interconnecting the drain terminals of the adjacent FET elements; resistors each interconnectors the source terminal of each of said FET elements and the ground; capacitors each having a first capacitor connected in parallel to said resistor between one section of the source terminal of each FET element and the ground and a second capacitor interconnecting the other section of the source terminal of each FET element and the ground; and a plurality of metal islands arranged alternately with said FET elements in a nearly straight line to be used for forming said first and second capacitors, each of said metal islands having a slit formed such as to separate said first and second capacitors formed on each of said metal islands, said resistors being connected between said metal islands and said one section of the source terminals of said FET elements.

Claim 26

A distributed FEET amplifier formed as a monolithic integrated circuit on a semiconductor substrate, comprising: an array of FET elements each having a gate terminal, a drain terminal and a source terminal having two sections; first inductor means interconnecting the gate terminals of the adjacent FET elements; second inductor means interconnecting the drain terminals of the adjacent FET elements; resistors each interconnectors the source terminal of each of said FET elements and the ground; capacitors each having a first capacitor connected in parallel to said resistor between one section of the source terminal of each FET element and the ground and a second capacitor interconnecting the other section of the source terminal of each FET element and the ground; and a plurality of metal islands arranged alternately with said FET elements in a nearly straight line to be used for forming said first and second capacitors, each of said metal islands having a slit formed such as to separate said first and second capacitors formed on each of said metal islands, said resistors being connected between said metal islands and said one section of the source terminals of said FET elements.

Claim 27

An amplifier as claimed in claim 20, wherein said slits are formed in the direction perpendicular to the direction of said array, the length of the slits is smaller than that of one side of said metal islands perpendicular to the direction of said array, thereby constituting two portions in each of said metal islands.

Claim 28

An amplifier as claimed in claim 21, wherein each of said resistors is connected between one of said two portions and the source terminal of said one section of the adjacent FET elements.

Claim 29

An amplifier as claimed in claim 21, wherein each of said resistors comprises a first resistor interconnecting one of said two portions and the source terminal of one of said adjacent FET elements and a second resistor interconnecting the other of said two portions and the source terminal of the other of said adjacent FET elements.

Claim 30

A bias voltage supply circuit for supplying a bias voltage to an electric circuit such as a distributed FET amplifier, said supply circuit comprising: an input terminal connected to a voltage source; an output terminal connected to said electric circuit for supplying a bias voltage thereto; a first lumped constant line means, one end thereof being connected to said input terminal and grounded through a capacitor; a second lumped constant line means, one end thereof being open and the other end thereof being connected to the other end of said first lumped constant line means and to said output terminal; and at least one circuit including a resistor connected between a point on said first lumped constant line means and a point on said second lumped constant line means.

Claim 31

A bias voltage supply circuit for supplying a bias voltage to an electric circuit such as a distributed FET amplifier, said supply circuit comprising: an input terminal connected to a voltage source; an output terminal connected to said electric circuit for supplying a bias voltage thereto; a first lumped constant line means, one end thereof being connected to said input terminal and grounded through a capacitor; a second lumped constant line means, one end thereof being open and the other end thereof being connected to the other end of said first lumped constant line means and to said output terminal; and at least one circuit including a resistor connected between a point on said first lumped constant line means and a point on said second lumped constant line means.

Claim 32

A supply circuit as claimed in claim 24, wherein said first and second lumped constant line means comprise inductors and capacitors.

Claim 33

In a distributed FET amplifier having an input terminal and an output terminal and including an array of FET elements each having a gate terminal, a drain and a source terminal, first inductor means interconnecting the gate terminals of the adjacent FET elements, second inductor means interconnecting the drain terminals of the adjacent FET elements, capacitor means having a capacitance greater than the gate-source capacitance of each of said FET elements, an inductance element, and means coupling the capacitor means and inductance element in parallel between the source terminal of each of said FET elements and a voltage reference.

Claim 34

In a distributed FET amplifier having an input terminal and an output terminal and including an array of FET elements each having a gate terminal, a drain and a source terminal, first inductor means interconnecting the gate terminals of the adjacent FET elements, second inductor means interconnecting the drain terminals of the adjacent FET elements, capacitor means having a capacitance greater than the gate-source capacitance of each of said FET elements, an inductance element, and means coupling the capacitor means and inductance element in parallel between the source terminal of each of said FET elements and a voltage reference.

Claim 35

An amplifier as claimed in claim 26 wherein said inductance element comprises a distributed constant line.

Claim 36

An amplifier as claimed in claim 26 wherein said capacitor means has a capacitance several times as large as said gate-source capacitance and produces a reactance much smaller than that produced by said inductance element for grounding the direct current in a used frequency.

Claim 37

An amplifier as claimed in claim 26 wherein said inductance element comprises a series combination comprising an inductance element and a resistor, and further comprising a first terminating means comprising a resistor and a capacitor connected in series between the terminal to which a drain bias is applied and ground, and a second terminating means comprising a resistor for grounding the direct current.