US4852049A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vector mask operation control unit
Assignee: NEC Corp
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Filing: 1986-07-30
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Granted: 1989-07-25
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Expires: 2006-07-30
Abstract
Abstract A vector mask control unit and method of operating same prevents the unnecessary reading or arithmetic operation of operands corresponding to mask inhibitory bits by generating a total address increment value based on the number of consecutive operation-inhibitory bits counted by a counter, the total address increment value being composed of at least one increment value that is multiplied by a power of two. The total address increment value is added to a vector address to obtain an operand address. As a result, the efficient procession of masked vector instructions can be easily achieved.
Inventors
- 👤 Noriaki Sakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:25
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8084; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30018; G06F9/30036; G06F9/30038
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
144 words
A vector mask operation control unit in a data processing system for executing processing of masked, vector instructions decoded by an instruction control unit comprising: counting means for counting consecutive operation-inhibitory bits in a plurality of bits, each operation-inhibitory bit masking one of a plurality of vector operands pointed to by said vector instructions decoded by said instruction unit; means for preventing memory access and arithmetic operations on said masked operands comprising: (a) increment generating means for generating a total address increment value in response to the count of consecutive operation-inhibitory bits counted by said counter means, said total address increment value being comprised of at least one address increment value multiplied by a power of two; and (b) address generating means for obtaining an operand address by adding the total address increment value received from said increment generating means, and a vector address.
Claim 2
Dependent Claim
144 words
A vector mask operation control unit in a data processing system for executing processing of masked, vector instructions decoded by an instruction control unit comprising: counting means for counting consecutive operation-inhibitory bits in a plurality of bits, each operation-inhibitory bit masking one of a plurality of vector operands pointed to by said vector instructions decoded by said instruction unit; means for preventing memory access and arithmetic operations on said masked operands comprising: (a) increment generating means for generating a total address increment value in response to the count of consecutive operation-inhibitory bits counted by said counter means, said total address increment value being comprised of at least one address increment value multiplied by a power of two; and (b) address generating means for obtaining an operand address by adding the total address increment value received from said increment generating means, and a vector address.
Claim 3
Dependent Claim
23 words
A vector mask control unit as claimed in claim 1, wherein said increment generating means comprises first and second 2 n -multiple-generating circuits.
Claim 4
Dependent Claim
55 words
A vector mask control unit as claimed in claim 2, wherein said first and second 2 n -multiple-generating circuits comprise a plurality of shifting means, each shifting means being capable of shifting bits representing a binary number a fixed number of positions to effect a multiplication of the binary number by a power of two.
Claim 5
Dependent Claim
70 words
A vector mask control unit as claimed in claim 3, further comprising a logic circuit including means for selecting one of said plurality of shifting means from each of said first and second 2 n -multiple-generating circuits in response to receiving the number of consecutive operation-inhibitory bits counted by said counting means and means for generating said address increment value in accordance with the output of said selected shifting means.
Claim 6
Independent Claim
140 words
A method of operating a vector mask control unit in a data processing system for processing masked vector instructions decoded by an instruction control unit, said method comprising the steps of: (a) counting operation-inhibitory bits in a plurality of bits with a counting means, each operation-inhibitory bit masking one of plural vector operands pointed to by said vector instructions decoded by said instruction unit; (b) preventing memory access and arithmetic operations on said inhibited vector operands by the further steps of: (1) generating a total address increment value by the use of the count of consecutive operation-inhibitory bits counted by said counter means, said total address increment value being comprised of at least one address increment value multiplied by a power of two, and (2) adding said total address increment value and a vector address to obtain an operand address.
Claim 7
Independent Claim
140 words
A method of operating a vector mask control unit in a data processing system for processing masked vector instructions decoded by an instruction control unit, said method comprising the steps of: (a) counting operation-inhibitory bits in a plurality of bits with a counting means, each operation-inhibitory bit masking one of plural vector operands pointed to by said vector instructions decoded by said instruction unit; (b) preventing memory access and arithmetic operations on said inhibited vector operands by the further steps of: (1) generating a total address increment value by the use of the count of consecutive operation-inhibitory bits counted by said counter means, said total address increment value being comprised of at least one address increment value multiplied by a power of two, and (2) adding said total address increment value and a vector address to obtain an operand address.
References Cited (Backward Citations)
US4179737A
Cited
US4680730A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-24 | 1993-01-23 | 1993-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-24 | 1997-01-23 | 1997-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-24 | 2001-01-23 | 2001-07-25 | $7700.00 | Window Closed / Lapsed |