US4851904A
Expired / Lapsed
US
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Motion detecting circuit for digital video signal
Assignee: Toshiba Corp
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Filing: 1988-03-11
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Granted: 1989-07-25
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Expires: 2008-03-11
Abstract
Abstract A frame memory stores one-frame data of an input digital video signal and outputs the stored data as a one-frame delayed digital video signal. A first motion data generator receives the input digital video signal and the one-frame delayed digital signal from the frame memory and generates first motion data in accordance with the difference between these two signals. A data compander receives the one-frame delayed digital video signal from the frame memory, compands the data amount of the one-frame delayed digital video signal, and oututs the resultant signal. A sub-frame memory stores the output signa from the data compander and outputs the stored data as a two-frame delayed signal. A data expander receives the two-frame delayed output signal from the sub-frame memory, expands the two-frame delayed output signal to the original data amount, and outputs the resultant signal. A second motion data generator receives the input digital video signal and the two-frame delayed signal from the data expander, and generates second motion data in accordance with the difference between the two signals.
Inventors
- 👤 Toru Miyazaki
- 👤 Kiyoyuki Kawai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:46
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/77; H04N9/78; H04N5/00; H04N5/14; H04N5/144
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
236 words
A motion detecting circuit for a digital video signal, said circuit comprising: frame memory means for storing one-frame data of an input digital video signal and outputting the stored data as a one-frame delayed digital video signal; first motion data generating means for receiving the input digital video signal and the one-frame delayed digital signal from said frame memory means, and generating first motion data in accordance with a difference between these signals; data companding means for receiving the one-frame delayed digital video signal from said frame memory means, companding a data amount of the one-frame delayed digital video signal, and outputting a resultant signal; sub-frame memory means for storing the output signal from said data companding means and outputting the stored data as a two-frame delayed signal; data expanding means for receiving the two-frame delayed output signal from said sub-frame memory means, expanding the two-frame delayed output signal to an original data amount, and outputting a resultant signal; section motion data generating means for receiving the input digital video signal and said resultant signal from said data expanding means, and generating second motion data in accordance with a difference between both of the signals; and motion-detecting signal generating means for respectively receiving the first and second motion data from said first and second motion data generating means and generating a motion detection signal by performing a predetermined operation between the first and second motion data.
Claim 2
Dependent Claim
236 words
A motion detecting circuit for a digital video signal, said circuit comprising: frame memory means for storing one-frame data of an input digital video signal and outputting the stored data as a one-frame delayed digital video signal; first motion data generating means for receiving the input digital video signal and the one-frame delayed digital signal from said frame memory means, and generating first motion data in accordance with a difference between these signals; data companding means for receiving the one-frame delayed digital video signal from said frame memory means, companding a data amount of the one-frame delayed digital video signal, and outputting a resultant signal; sub-frame memory means for storing the output signal from said data companding means and outputting the stored data as a two-frame delayed signal; data expanding means for receiving the two-frame delayed output signal from said sub-frame memory means, expanding the two-frame delayed output signal to an original data amount, and outputting a resultant signal; section motion data generating means for receiving the input digital video signal and said resultant signal from said data expanding means, and generating second motion data in accordance with a difference between both of the signals; and motion-detecting signal generating means for respectively receiving the first and second motion data from said first and second motion data generating means and generating a motion detection signal by performing a predetermined operation between the first and second motion data.
Claim 3
Dependent Claim
30 words
A circuit according to claim 1, wherein said first motion data generating means includes a low-pass filter for removing a chrominance signal component included in the input digital video signal.
Claim 4
Dependent Claim
15 words
A circuit according to claim 1, wherein said data companding means includes a sub-sample circuit.
Claim 5
Dependent Claim
15 words
A circuit according to claim 1, wherein said data expanding means includes an interpolation filter.
Claim 6
Dependent Claim
20 words
A circuit according to claim 4, wherein said interpolation filter includes a unit delay element, an adder, and a selector.
Claim 7
Dependent Claim
271 words
A motion detecting circuit for a digital video signal, said circuit comprising: frame memory means for storing one-frame data of an input digital video signal and outputting the stored data as a one-frame delayed digital video signal; first motion data generating means for receiving the input digital video signal and the one-frame delayed digital signal from said frame memory means, and generating first motion data in accordance with the difference between these two signals. first data companding means for receiving the input digital video signal, companding a data amount thereof and outputting a resultant signal; second data companding means for receiving the one-frame delayed digital video signal from said frame memory means, companding a data amount thereof, and outputting a resultant signal; sub-frame memory means for storing the output signal from said second data companding means and outputting the stored data as a two-framed delayed signal; second motion data generating means for receiving the output signal from said first data companding means and the two-frame delayed signal from said sub-frame memory means and generating second motion data which corresponds to a difference between the two signals; data expanding means for receiving the second motion data from said second motion data generating means, expanding the second motion data to an original data amount of the input digital video signal, and outputting a resultant signal; and motion-detecting signal generating means for receiving the first motion data generated by said first motion data generating means and the second motion data expand by said data expanding means and generating a motion detecting signal by performing a predetermined operation between the first and second motion data.
Claim 8
Dependent Claim
271 words
A motion detecting circuit for a digital video signal, said circuit comprising: frame memory means for storing one-frame data of an input digital video signal and outputting the stored data as a one-frame delayed digital video signal; first motion data generating means for receiving the input digital video signal and the one-frame delayed digital signal from said frame memory means, and generating first motion data in accordance with the difference between these two signals. first data companding means for receiving the input digital video signal, companding a data amount thereof and outputting a resultant signal; second data companding means for receiving the one-frame delayed digital video signal from said frame memory means, companding a data amount thereof, and outputting a resultant signal; sub-frame memory means for storing the output signal from said second data companding means and outputting the stored data as a two-framed delayed signal; second motion data generating means for receiving the output signal from said first data companding means and the two-frame delayed signal from said sub-frame memory means and generating second motion data which corresponds to a difference between the two signals; data expanding means for receiving the second motion data from said second motion data generating means, expanding the second motion data to an original data amount of the input digital video signal, and outputting a resultant signal; and motion-detecting signal generating means for receiving the first motion data generated by said first motion data generating means and the second motion data expand by said data expanding means and generating a motion detecting signal by performing a predetermined operation between the first and second motion data.
Claim 9
Dependent Claim
30 words
A circuit according to claim 6, wherein said first motion data generating means includes a low-pass filter for removing a chrominance signal component included in the input digital video signal.
Claim 10
Dependent Claim
20 words
A circuit according to claim 6, wherein each of said first and second data companding means includes a sub-sample circuit.
Claim 11
Dependent Claim
15 words
A circuit according to claim 6, wherein said data expanding means includes an interpolation filter.
Claim 12
Dependent Claim
20 words
A circuit according to claim 9, wherein said interpolation filter includes a unit delay element, an adder, and a selector.
Claim 13
Dependent Claim
369 words
A motion detecting circuit for a digital video signal, said circuit comprising: frame memory means for storing one-frame data of an input digital video signal and outputting the stored data as a one-frame delayed digital video signal; first low-pass filter means for filtering the one-frame delayed digital video signal from said frame memory means; second low-pass filter means for filtering the input digital video signal; first motion data generating means for receiving the output signals from said first and second low-pass filter means and generating first motion data in accordance with the difference between the two signals; first synthesizing means for receiving the one-frame delayed digital signal from said frame memory means and the output signal from said first low-pass filter means and generating a first predetermined component signal; second synthesizing means for receiving the input digital video signal and the output signal from said second low-pass filter means, and outputting a second predetermined component signal; first data companding means for receiving the first predetermined component signal from said first synthesizing means, companding a data amount of the first predetermined component signal, and outputting a resultant signal; second data companding means for receiving the second predetermined component signal from said second synthesizing means, companding a data amount of the second predetermined component signal, and outputting a resultant signal; sub-frame memory means for storing the output signal from said first data companding means and outputting the stored data as a two-frame delayed signal; second motion data generating means for receiving the output signal from said second data companding means and the two-frame delayed signal from said sub-frame memory means and generating second motion data which corresponds to a difference between both of the signals; data expanding means for receiving the second motion data from said second motion data generating means, expanding the second motion data to an original data amount of the input digital video signal, and outputting a resultant signal; and motion-detecting signal generating means for receiving the first motion data generated by said first motion data generating means and the second motion data from said second motion data generating means and generating a motion detection signal by performing a predetermined operation between the first and second motion data.
Claim 14
Dependent Claim
369 words
A motion detecting circuit for a digital video signal, said circuit comprising: frame memory means for storing one-frame data of an input digital video signal and outputting the stored data as a one-frame delayed digital video signal; first low-pass filter means for filtering the one-frame delayed digital video signal from said frame memory means; second low-pass filter means for filtering the input digital video signal; first motion data generating means for receiving the output signals from said first and second low-pass filter means and generating first motion data in accordance with the difference between the two signals; first synthesizing means for receiving the one-frame delayed digital signal from said frame memory means and the output signal from said first low-pass filter means and generating a first predetermined component signal; second synthesizing means for receiving the input digital video signal and the output signal from said second low-pass filter means, and outputting a second predetermined component signal; first data companding means for receiving the first predetermined component signal from said first synthesizing means, companding a data amount of the first predetermined component signal, and outputting a resultant signal; second data companding means for receiving the second predetermined component signal from said second synthesizing means, companding a data amount of the second predetermined component signal, and outputting a resultant signal; sub-frame memory means for storing the output signal from said first data companding means and outputting the stored data as a two-frame delayed signal; second motion data generating means for receiving the output signal from said second data companding means and the two-frame delayed signal from said sub-frame memory means and generating second motion data which corresponds to a difference between both of the signals; data expanding means for receiving the second motion data from said second motion data generating means, expanding the second motion data to an original data amount of the input digital video signal, and outputting a resultant signal; and motion-detecting signal generating means for receiving the first motion data generated by said first motion data generating means and the second motion data from said second motion data generating means and generating a motion detection signal by performing a predetermined operation between the first and second motion data.
Claim 15
Dependent Claim
20 words
A circuit according to claim 11, wherein each of said first and second data companding means includes a sub-sample circuit.
Claim 16
Dependent Claim
15 words
A circuit according to claim 11, wherein said data expanding means includes an interpolation filter.
Claim 17
Dependent Claim
20 words
A circuit according to claim 13, wherein said interpolation filter includes a unit delay element, an adder, and a selector.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-24 | 1993-01-23 | 1993-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-24 | 1997-01-23 | 1997-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-24 | 2001-01-23 | 2001-07-25 | $7700.00 | Window Closed / Lapsed |