Multistage switching system for switching N1 input channels to N2 output channels

Claim 1

A switching system for switching N 1 input channels to N 2 output channels, comprising an input stage, at least one intermediate stage and an output stage in which the input stage is arranged for providing a multiple connection with multiplicity M of each input channel to the inputs of the intermediate stage in accordance with a given distribution rule, in which the connection distribution of an input channel is independent of the routing of that channel by the switching system, in which the output stage is composed of r, where r≧1, sub-coupling fields each having n 2 outputs, where N 2 =rn 2 ; and in which the intermediate stage is in the form of a space-division switching stage having M×N 1 incoming channels; characterized in that the input stage is formed by a number of m, where m≧2, parallel input time-division stages to each of which n 1 input channels are connected, so that m×n 1 =N 1 , those input time-division multiplex switching stages each being conducted individually via its own output conductor to an associated input of the intermediate stage for applying M×N 1 time channels thereto, the input time-division switching stages each including a control memory having a first memory portion whose content is determined by the predetermined distribution instruction, in that the multiplicity M is less than or equal to the number of input time-division switching stages m, that the intermediate stage is constituted by a space-division switching stage having m inputs and r outputs which are switched at the rate of the input time-division switching stages, the space-division multiplex circuit including a routing memory whose content is determined by the routing of the channels to be switched through, and in that each output sub-coupling field is constituted by an output time-division multiplex switching stage having n 2 output channels, which is connected via its own conductor to an associated output of the intermediate stage, the output switching stages each including a routing memory whose content is determined by the routing of the channels to be switched through.