Bipolar programmable logic array

Claim 2

A bipolar programmable logic array having a current source which is compensated for temperature variations comprising: a plurality of input buffer/inverters (INV1 . . . INVn), each of said plurality of input buffer/inverts having an input, for receiving an input logic signal, and an output; a plurality of diodes (D1 . . . Dn), each of said plurality of diodes having its cathode connected to a respective output of a corresponding input buffer/inverter and its anode coupled to a common sense line (16); a sense amplifier/output buffer (SA) having its input connected to the common sense line (16) and its output connected to an output terminal; a current source (IS) being formed of a PNP-type transistor (Q11) and a resistor (R12), said transistor having its emitter coupled to a supply potential via said resistor (R12) and its collector connected to the common sense line (16); said current source transistor (Q11) charging said common senses line to a high logic level when all of the input logic signals are in a low logic level; bandgap circuit means (14) for generating a first temperature-dependent reference voltage (VBB), said transistor having its base connected to receive said first temperature-dependent reference voltage; and wherein a second temperature-dependent reference voltage (Vref(R12)) proportional to said first temperature-dependent reference voltage is generated across said resistor (R12) which increases proportional to the increasing values of said resistor (R12) over temperature so that the current flowing through said current source transistor (Q11) remains substantially constant.

Claim 3

A logic array as claimed in claim 1, wherein said plurality of diodes comprise Schottky didoes (D1 . . . Dn).

Claim 4

A logic array as claimed in claim 1, wherein the temperature variations are between -55° C. and +155° C.

Claim 5

A logic array as claimed in claim 1, wherein said logic array is formed as an integrated circuit on a single semiconductor chip.

Claim 6

A logic array as claimed in claim 1, further comprising a plurality of blowable fuses (F1 . . . Fn), each fuse being interconnected between a respective anode of a corresponding diode (D1 . . . Dn) and the common sense line 16, each of said fuses being selectively blown during programming to provide a desired logic function.

Claim 7

A logic array as claimed in claim 5, wherein said fuses (F1 . . . Fn) are formed of one of a polysilicon material, silicide, and metal.

Claim 8

A logic array as claimed in claim 6, wherein said fuses (F1 . . . Fn) are blown by one of a programming current and laser cut.

Claim 9

A bipolar programmable logic array having a current source which is compensated for temperature variations comprising: a plurality of input buffer/inverters (INV1 . . . INVn), each of said plurality of input buffer/inverters having an input, for receiving an input logic signal, and an output; a plurality of transistors (Q13 . . . Qn), each of said plurality of transistors having its base connected to the respective outputs of said input buffer/inverters, its collector connected to a supply potential and its emitter coupled to a common sense line (16); a sense amplifier/output buffer (SA) having its input connected to the common sense line (16) and its output connected to an output terminal; a current source (IS) being formed of an NPN-type transistor (Q12) and a resistor (R13), said current source transistor having its emitter coupled to the ground potential via said resistor (R13) and its collector connected to the common sense line (16); said current source transistor (Q12) discharging said common sense line to a low logic level when all of the input logic signals are in a high logic level; bandgap circuit means (14) for generating a first temperature-dependent reference voltage (VCS), said current source transistor (Q12) having its base connected to receive said first temperature-dependent reference voltage; and wherein a second temperature-dependent reference voltage (Vref(R13)) proportional to said first temperature-dependent reference voltage is generated across said resistor (R13) which increases proportional to the increasing values of said resistor (R13) over temperature so that the current flowing through said current source transistor remains substantially constant.

Claim 10

A bipolar programmable logic array having a current source which is compensated for temperature variations comprising: a plurality of input buffer/inverters (INV1 . . . INVn), each of said plurality of input buffer/inverters having an input, for receiving an input logic signal, and an output; a plurality of transistors (Q13 . . . Qn), each of said plurality of transistors having its base connected to the respective outputs of said input buffer/inverters, its collector connected to a supply potential and its emitter coupled to a common sense line (16); a sense amplifier/output buffer (SA) having its input connected to the common sense line (16) and its output connected to an output terminal; a current source (IS) being formed of an NPN-type transistor (Q12) and a resistor (R13), said current source transistor having its emitter coupled to the ground potential via said resistor (R13) and its collector connected to the common sense line (16); said current source transistor (Q12) discharging said common sense line to a low logic level when all of the input logic signals are in a high logic level; bandgap circuit means (14) for generating a first temperature-dependent reference voltage (VCS), said current source transistor (Q12) having its base connected to receive said first temperature-dependent reference voltage; and wherein a second temperature-dependent reference voltage (Vref(R13)) proportional to said first temperature-dependent reference voltage is generated across said resistor (R13) which increases proportional to the increasing values of said resistor (R13) over temperature so that the current flowing through said current source transistor remains substantially constant.

Claim 11

A logic array as claimed in claim 8, wherein said plurality of transistors (Q13 . . . Qn) are of the NPN-type conductivity.

Claim 12

A logic array as claimed in claim 8, wherein the temperature variations are between -55° C. and +155° C.

Claim 13

A logic array as claimed in claim 8, wherein said logic array is formed as an integrated circuit on a single semiconductor chip.

Claim 14

A logic array as claimed in claim 8, further comprising a plurality of blowable fuses (F1 . . . Fn), each fuse being interconnected between a respective emitter of a corresponding one of said plurality of transistors and the common sense line (16), each of said fuses being selectively blown during programming to provide a desired logic function.

Claim 15

A logic array as claimed in claim 12, wherein said fuses (F1 . . . Fn) are formed of one of a polysilicon material, silicide, and metal.

Claim 16

A logic array as claimed in claim 13, wherein said fuses (F1 . . . Fn) are blown by one of a programming current and laser cut.