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US4847742A Expired / Lapsed US ⏱️ 0.0 years remaining

Multi-channel inverter circuit

Assignee: Hitachi Ltd
•
Filing: 1988-02-08
•
Granted: 1989-07-11
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Expires: 2008-02-08
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Abstract

Abstract The invention is to provide a more economical and practical multi-channel inverter with reference particularly to a modulation process of the time width, wherein a DC output is fed to each of a multiplicity of output channel circuits through time division to a multi-channeling, each of the time widths is modulated pertinently according to each output, thereby obtaining DC and AC multi-channel outputs independently of each other between said channels.

Inventors

  • 👤 Shin-ichi Ohashi
  • 👤 Isao Fukushima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 04:08
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/33561; H02M3/33569; H02M3/33571

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 119 words
A multi-channel inverter circuit, comprising a primary circuit equipped with a primary power supply, a primary inductance and a primary switching means; a secondary circuit comprising a secondary inductance coupled inductively to said primary inductance, and a plurality of output channel circuits each having a first capacitor, a secondary switching means and a load circuit provided at least at each said output channel circuit; wherein electrical energy generated on said primary circuit is transferred in sequence to the load circuit provided at every output channel circuit of said second circuit through a coupling of said primary inductance and secondary inductance, in a sum total of switching time width determined for the output channel circuits by the primary switching means.
Claim 2
Dependent Claim 119 words
A multi-channel inverter circuit, comprising a primary circuit equipped with a primary power supply, a primary inductance and a primary switching means; a secondary circuit comprising a secondary inductance coupled inductively to said primary inductance, and a plurality of output channel circuits each having a first capacitor, a secondary switching means and a load circuit provided at least at each said output channel circuit; wherein electrical energy generated on said primary circuit is transferred in sequence to the load circuit provided at every output channel circuit of said second circuit through a coupling of said primary inductance and secondary inductance, in a sum total of switching time width determined for the output channel circuits by the primary switching means.
Claim 3
Dependent Claim 70 words
A multi-channel inverter circuit as defined in claim 1, wherein an input voltage of the secondary circuit and a control voltage for controlling the secondary switching means are compared at the output channel circuits, the switching time width of said secondary switching means being controlled according to a comparison output at the output channel circuits, outputs of said secondary circuit being fed to the load of the output channel circuits.
Claim 4
Dependent Claim 46 words
A multi-channel inverter circuit as defined in claim 2, wherein a signalling means for comparing an input voltage of said secondary circuit with a control voltage for controlling the secondary switching means at the output channel circuits to control the secondary switching means comprises a comparator.
Claim 5
Dependent Claim 74 words
A multi-channel inverter circuit as defined in claim 1, further comprising a means for controlling a switching time of the primary circuit through a coupled circuit on an end voltage of a second capacitor of the secondary circuit, the first capacitor and the load circuit connected in parallel to said second capacitor at the output channel circuit, and a circuit of a diode in series with the second capacitor parallely connected with a resistance.
Claim 6
Dependent Claim 50 words
A multi-channel inverter circuit as defined in claim 1, further comprising a detecting circuit for detecting a peak value of a rectifier output voltage of the multi-channel inverter circuit, and a means for controlling a switching time of said primary circuit according to the output voltage of said detecting circuit.
Claim 7
Dependent Claim 44 words
A multi-channel inverter circuit as defined in claim 1, further comprising an amplifier with the secondary circuit comprising a capacitor and a load at the output channel circuits, outputs resulting from rectification of said secondary circuit input being connected to each of said amplifiers.
Claim 8
Dependent Claim 58 words
A multi-channel inverter as defined in claim 1, further comprising a peak value detection circuit for detecting the peak value of a rectifier output voltage of said secondary circuit, a switching circuit for short-circuiting said rectifier output terminal, and a means for driving said rectifier output short-circuit switching circuit on a output of said peak value detection circuit.
Claim 9
Dependent Claim 61 words
A multi-channel inverter circuit as defined in claim 1, wherein a plurality of switching time widths of the primary switching means are determined through summarily changing in sequence by means of a differential voltage comparison obtained through comparing an output voltage of the output channel circuits in the secondary circuit with an input signal voltage supplied to the output channel circuits.
Claim 10
Dependent Claim 68 words
A multi-channel inverter circuit as defined in claim 1, wherein the secondary switching means includes means for obtaining outputs through synchronizing with the primary circuit and rectifying the secondary inductance voltage, comprising a push-pull circuit means to the primary switching means and the secondary switching means, the push-pull circuit means being provided with a switching change-over circuit for selectively operating a switching circuit of said push-pull circuit means.

References Cited (Backward Citations)

US4034232A Cited
US4122514A Cited
US4055790A Cited
JPS54140153A Cited
US4672516A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-07-10 1993-01-09 1993-07-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-07-10 1997-01-09 1997-07-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-07-10 2001-01-09 2001-07-11 $7700.00 Window Closed / Lapsed

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