US4847613A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data transfer apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1987-07-14
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Granted: 1989-07-11
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Expires: 2007-07-14
Abstract
Abstract In a data transfer apparatus, as one substation in a loop type signal transfer system, e.g. for use in an automatic machine, synchronization information and address information are received and the address is checked by an address coincidence circuit; when address coincidence is detected the data information in the received signal is replaced by serialized data which is contrived by parallel-serial conversion of the parallel input data at the substation; therefore there is no need of once storing the entire received signal transferred, and therefore, high speed data transfer results.
Inventors
- 👤 Tutomu Sakurai
- 👤 Keishiro Ota
- 👤 Saburo Kubota
- 👤 Masanobu Miyata
- 👤 Hiroshi Fujiwara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:10
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/427; H04L12/433
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
174 words
A data transfer apparatus comprising: an address coincidence circuit for detecting coincidence of address information included in a transfer signal consisting of synchronization information, said address information and data information, by comparing said address information with a predetermined address, and for memorizing said coincidence and issuing a coincidence signal, a synchronized carrier generator for generating carrier signal which is corresponding to transfer speed of said transfer signal, a parallel-serial converter for converting parallel data information to serial signal by using said carrier signal issued from said synchronized carrier generator as latch-timing signal, a delay circuit for delaying said transfer signal in a manner that the part of time period of said data information in said transfer signal is issued at the same time period that said serial signal is issued, and a switch circuit for switching to insert said serial signal given thereto in place of said data information in said transfer signal given thereto through said delay circuit during a period when said coincidence signal is being given from said address coincidence circuit.
Claim 2
Dependent Claim
174 words
A data transfer apparatus comprising: an address coincidence circuit for detecting coincidence of address information included in a transfer signal consisting of synchronization information, said address information and data information, by comparing said address information with a predetermined address, and for memorizing said coincidence and issuing a coincidence signal, a synchronized carrier generator for generating carrier signal which is corresponding to transfer speed of said transfer signal, a parallel-serial converter for converting parallel data information to serial signal by using said carrier signal issued from said synchronized carrier generator as latch-timing signal, a delay circuit for delaying said transfer signal in a manner that the part of time period of said data information in said transfer signal is issued at the same time period that said serial signal is issued, and a switch circuit for switching to insert said serial signal given thereto in place of said data information in said transfer signal given thereto through said delay circuit during a period when said coincidence signal is being given from said address coincidence circuit.
Claim 3
Dependent Claim
219 words
A data transfer apparatus comprising: an address coincidence circuit for detecting coincidence of address information included in a transfer signal consisting of synchronization information, said address information and data information, by comparing said address information with a predetermined address, and for memorizing said coincidence and issuing a coincidence signal, a synchronized carrier generator for generating carrier signal which is corresponding to transfer speed of said transfer signal, a serial-parallel converter for converting serial data information of received transfer signal into output parallel signal by using carrier signal issued from said synchronized carrier generator as conversion timing clock, an output latch circuit for latching output parallel signal converted from said serial signal by said serial-parallel converter, a parallel-serial converter for converting said output parallel signal to be issued from said output latch circuit into a serial data information, a delay circuit for delaying said transfer signal in a manner that the part of time period of said data information in said transfer signal is issued at the same time period that said serial signal is issued, and a switch circuit for switching to insert said serial signal given thereto in place of said data information in said transfer signal given thereto through said delay circuit during a period when said coincidence signal is being given from said address coincidence circuit.
Claim 4
Dependent Claim
219 words
A data transfer apparatus comprising: an address coincidence circuit for detecting coincidence of address information included in a transfer signal consisting of synchronization information, said address information and data information, by comparing said address information with a predetermined address, and for memorizing said coincidence and issuing a coincidence signal, a synchronized carrier generator for generating carrier signal which is corresponding to transfer speed of said transfer signal, a serial-parallel converter for converting serial data information of received transfer signal into output parallel signal by using carrier signal issued from said synchronized carrier generator as conversion timing clock, an output latch circuit for latching output parallel signal converted from said serial signal by said serial-parallel converter, a parallel-serial converter for converting said output parallel signal to be issued from said output latch circuit into a serial data information, a delay circuit for delaying said transfer signal in a manner that the part of time period of said data information in said transfer signal is issued at the same time period that said serial signal is issued, and a switch circuit for switching to insert said serial signal given thereto in place of said data information in said transfer signal given thereto through said delay circuit during a period when said coincidence signal is being given from said address coincidence circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |