Memory comprising simultaneously addressable memory elements

Claim 2

A memory comprising: a. an array of memory elements (1), defining at least one coordinate direction, which elements are simultaneously addressable at random in subarrays defined by at least one respective range of addresses along the at least one coordinate direciton; b. at least one selection means (8,9) for addressing a subarray (2) defined by at least one respective desired range of addresses in at least one respective one of the at least one coordinate direction, each selection means comprising: i. respective input means for receiving respective upper (X H ,Y H ) and lower (X L ,Y L ) limit information defining said respective desired range; ii. a respective plurality of similary-operating selection modules (11,12), arranged as nodes connecting branches in a vertical tree structure having a plurality of levels, each module being responsive to a part of said upper and lower limit information, each module corresponding to a respective module range of addresses, with the respective module range of addresses being smaller for modules at lower levels of the tree and having: A. a respective input for receiving an indication signal (BE, LE, RE, OR, IR) which provides a position indication for indicating a position of the part of the upper and lower limit information with respect to the respective module range of addresses, and B. a respective output means for supplying further indication signals such that in the modules at a lowest level of the tree structure the further indication signals are addressing signals for the memory elements in the subarray, and in the modules not at the lowest level of the tree structure the further indication signals are more specific position information for modules therebelow; whereby, granularity of selection of the memory elements is arbitrarily low.

Claim 3

The memory of claim 1 wherein a. each upper and lower limit information comprises respective first and second bit sequences; b. each of the modules comprises a respective second input means for receiving one bit from the respective first bit sequence and a corresponding bit from the respective second bit sequence; c. each of the modules not at the lowest level supplies two further indication signals to two respective selection modules at a lower level; and d. each of the modules at the lowest level supplies two addressing signals to relevant ones of the memory elements.

Claim 4

The memory of claim 2 wherein a. the array of memory elements defines and is addressable in first and second coordinate directions; and b. there are first and second selection means for addressing a subarray which is defined by first and second respective first and second desired ranges of memory elements in the first and second coordinate directions and the respective input means of each selection means is for receiving respective upper and lower limit information for a respective one of the first and second desired ranges.

Claim 5

The memory of claim 1 wherein a. the array of memory elements defines and is addressable in first and second coordinate directions; and b. there are first and second selection means for addressing a subarray which is defined by first and second respective first and second desired ranges of memory elements in the first and second coordinate directions and the respective input means of each selection means is for receiving respective upper and lower limit information for a respective one of the first and second desired ranges.

Claim 6

The memory of claim 1 wherein each memory element comprises means for simultaneously gating the addressing signals from the lowest level of the tree structure to the memory elements, so that only the memory elements covered by a relevant desired range are activated.

Claim 7

The memory of claim 1 wherein all of the selection modules not on the lowest level are identical.

Claim 8

Memory apparatus comprising: a. a plurality of the memories as claimed in claim 1, 2, 4, 3, 5, or 6, arranged on chips into rows and/or columns and addressable by a further tree structure; and b. a plurality of further selection means acting as nodes in the further tree structure.

Claim 9

Memory apparatus comprising: a plurality of chips arranged in rows and/or columns, each chip comprising a memory which comprises: a. an array of memory elements, defining at least one coordinate direction, which elements are simultaneously addressable at random in subarrays defined by at least one respective range of addresses along the at least one coordinate direction; b. at least one selection means for addressing a subarray defined by at least one respective desired range of addresses in at least one respective on of the at least one coordinate direction, each selection means comprising: i. respective input means for receiving upper and lower limit information defining said respective desired range; ii. a respective plurality of similarly-operating selection modules, arranged as nodes connecting branches in a vertical tree structure having a plurality of levels, each module being responsive to a part of said upper and lower limit information, each module corresponding to a respective module range of addresses, with the respective module range of addresses being smaller for modules at lower levels of the tree and having: A. a respective input for receiving an indication signal which provides a position indication for indicating a position of the part of the upper and lower limit information with respect to the respective module range of addresses, and B. a respective output means for supplying further indication signals such that in the modules at a lowest level of the tree structure the further indication signals are addressing signals for the memory elements in the subarray, and in the modules not at the lowest level of the tree structure the further indication signals are more specific position information for modules therebelow; whereby, granularity of selection of the memory elements is arbitrarily low; and c. a further selection module coupled above the highest level in the tree structure; the chips being further arranged so that each of the further selection modules is a node in a further tree structure analogous to the tree structure of the individual selection means, and so that the further tree structure is obtained exclusively by external wiring together of the chips.

Claim 10

Memory apparatus comprising: a plurality of chips arranged in rows and/or columns, each chip comprising a memory which comprises: a. an array of memory elements, defining at least one coordinate direction, which elements are simultaneously addressable at random in subarrays defined by at least one respective range of addresses along the at least one coordinate direction; b. at least one selection means for addressing a subarray defined by at least one respective desired range of addresses in at least one respective on of the at least one coordinate direction, each selection means comprising: i. respective input means for receiving upper and lower limit information defining said respective desired range; ii. a respective plurality of similarly-operating selection modules, arranged as nodes connecting branches in a vertical tree structure having a plurality of levels, each module being responsive to a part of said upper and lower limit information, each module corresponding to a respective module range of addresses, with the respective module range of addresses being smaller for modules at lower levels of the tree and having: A. a respective input for receiving an indication signal which provides a position indication for indicating a position of the part of the upper and lower limit information with respect to the respective module range of addresses, and B. a respective output means for supplying further indication signals such that in the modules at a lowest level of the tree structure the further indication signals are addressing signals for the memory elements in the subarray, and in the modules not at the lowest level of the tree structure the further indication signals are more specific position information for modules therebelow; whereby, granularity of selection of the memory elements is arbitrarily low; and c. a further selection module coupled above the highest level in the tree structure; the chips being further arranged so that each of the further selection modules is a node in a further tree structure analogous to the tree structure of the individual selection means, and so that the further tree structure is obtained exclusively by external wiring together of the chips.