Time division channel switching circuit

Claim 2

In a time division channel switching circuit, in which a desired sub channel accommodated in a desired channel on an inputhighway, where n (an integer more than one) channels, each having m (an integer more than one) sub channels, have been time-division-multiplexed, is switched to a sub channel of a desired channel on a time-division-multiplexed output highway, the improvement comprising: a serial-to-parallel converter whereby the input highway is converted into a plurality m of internal highways equal in number to paralleled sub channels; time switches of the same number m as that of sub channels, each time switch having channel memories of the same number as that of sub channels and each channel memory having a memory capacity separated into a plurality of blocks equal to the number n of channels; selectors, each provided in correspondence to one of the time switches, for selecting a desired channel memory output of the corresponding time switch; and a parallel-to-serial converter for time division multiplexing the output of each selector into the output highway; wherein the internal highways are supplied to all the time switches in parallel; the contents of the desired same address are read out of the respective channel memories in one of the time switches and a desired one of the channel memory outputs is selected by one of the selectors in correspondence to said one of the time switches.

Claim 3

In a time division channel switching circuit, in which a desired sub channel accommodated in a desired channel on an input highway, where n (an integer more than one) channels, each having m (an integer more than one) sub channels, have been time-division-multiplexed, is switched to a sub channel of a desired channel on a time-division-multiplexed output highway, the improvement comprising: a serial-to-parallel converter whereby the input highway is converted into a plurality m of internal highways equal in number to paralleled sub channels; time switches of the same number m as that of sub channels, each time switch having channel memories of the same number m as that of sub channels and each channel memory having a memory capacity separated into a plurality of blocks equal to the number n of channels; selectors, each provided in correspondence to one of the time switches, for selecting a desired channel memory output of the corresponding time switch; a parallel-to-serial converter for time division multiplexing the output of each selector into the output highway; a counter for generating clock pulses for one n-th of the frame period T of said time-division multiplexing; and wherein the internal highways are supplied to all the time switches in parallel; the contents of the desired same address are read out of the respective channel memories in one of the time switches in synchronism with the clock pulses and a desired one of the channel memory outputs is selected in synchronism with the clock pulses by one of the selectors in correspondence to said one of the time switches.

Claim 4

In a time division channel switching circuit, in which a desired sub channel accommodated in a desired channel on an input highway, where n (an integer more than one) channels, each having m (an integer more than one) sub channels, have been time-division-multiplexed, is switched to a sub channel of a desired channel on a time-division-multiplexed output highway, the improvement comprising: a serial-to-parallel converter whereby the input highway is converted into a plurality m of internal highways equal in number to paralleled sub channels; time switches of the same number m as that of sub channels, each time switch having channel memories of the same number m as that of sub channels and each channel memory having a memory capacity separated into a plurality of blocks equal to the number n of channels; selectors, each provided in correspondence to one of the time switches, for selecting a desired channel memory output of the corresponding time switch; a parallel-to-serial converter for time division multiplexing the output of each selector into the output highway; a counter for generating clock pulses for one n-th of the frame period T of said time-division multiplexing; and wherein the internal highways are supplied to all the time switches in parallel; the contents of the desired same address are read out of the respective channel memories in one of the time switches in synchronism with the clock pulses and a desired one of the channel memory outputs is selected in synchronism with the clock pulses by one of the selectors in correspondence to said one of the time switches.

Claim 5

A time division channel switching circuit according to claim 2, including a gate control memory to which said clock pulses are applied, and wherein each of the selectors comprises a gate circuit connected to said one of the time switches for receiving the desired channel memory output of the corresponding time switch and for providing the output of each selector under control of said gate control memory, to which said clock pulses are applied.