US4841437A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System architecture for a test apparatus having primary and dependent processors
Assignee: LP Com
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Filing: 1985-09-18
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Granted: 1989-06-20
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Expires: 2005-09-18
Abstract
Abstract A multifunction test apparatus which is capable of performing total communication network measurments and includes a primary processor linked to a number of dependent processors. The primary processor plays a number of different roles in the functioning of the test system, which roles require substantial interaction between the primary processor and dependent processors. In some test configurations, the primary processor becomes a dependent processor. In other configurations, the primary processor is timeplexed and interleaved with the operation of the dependent processors in performing subfunctions for the dependent processors. The architecture also provides for direct communication and resource sharing between the dependent processors. In another aspect of the subject invention, the primary processor performs overflow calculations for the dependent processors. Finally, the device is arranged such that all test functions are displayed with consistent screen formats.
Inventors
- 👤 Andre Lubarsky
- 👤 Richard E. Pospisil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:12
CPC Classifications
H; H04; H04L; H04L43/00; H04L43/50; G; G06; G06F; G06F11/00; G06F11/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
159 words
An apparatus for analyzing communication lines, comprising: a primary processor; a digital information bus; a dependent processor for digitally processing analog singals, said dependent processor being connected to said primary processor via said digital information bus; an analog information bus; and an interface module connected to said primary processor via said digital information bus and to said dependent processor via said analog information bus, said interface module having a means to connect said interface module to the communications lines to be analyzed so that the interface module may send analog signals to the communications lines and the interface module may receive analog signals from the communications lines, wherein the primary processor controls the signals passing between the interface module and the communications lines by sending digital instructions to both said dependent processor and said interface module via said digital information bus, and wherein said dependent processor and said interface module communicate using analog signals via said analog information bus.
Claim 2
Independent Claim
159 words
An apparatus for analyzing communication lines, comprising: a primary processor; a digital information bus; a dependent processor for digitally processing analog singals, said dependent processor being connected to said primary processor via said digital information bus; an analog information bus; and an interface module connected to said primary processor via said digital information bus and to said dependent processor via said analog information bus, said interface module having a means to connect said interface module to the communications lines to be analyzed so that the interface module may send analog signals to the communications lines and the interface module may receive analog signals from the communications lines, wherein the primary processor controls the signals passing between the interface module and the communications lines by sending digital instructions to both said dependent processor and said interface module via said digital information bus, and wherein said dependent processor and said interface module communicate using analog signals via said analog information bus.
Claim 3
Independent Claim
58 words
An apparatus for analyzing communication lines comprising: a primary processor; a digital information bus; a first dependent processor connected to said primary processor via said digital information bus; a second dependent processor connected to said primary processor via said digital information bus; and an interface bus connecting said first and second dependent processors thereby allowing direct communication therebetween.
Claim 4
Independent Claim
58 words
An apparatus for analyzing communication lines comprising: a primary processor; a digital information bus; a first dependent processor connected to said primary processor via said digital information bus; a second dependent processor connected to said primary processor via said digital information bus; and an interface bus connecting said first and second dependent processors thereby allowing direct communication therebetween.
Claim 5
Independent Claim
122 words
An apparatus for analyzing communication lines, comprising: a primary processor; a dependent processor for receiving analog signals from the communications lines to be analyzed, digitally processing the received analog signals, and sending other analog signals to the communciations lines; and a digital information bus connecting said dependent processor to said primary processor, wherein said primary processor provides instructions to said dependent processor over the digital information bus, for controlling the manner in which the dependent processor processes analog signals, wherein said dependent processor provides data to said primary processor over the digital information bus, and wherein the primary processor performs overflow calculations using the data received from the dependent processor to increase the speed of the functions performed by said dependent processor."
Claim 6
Independent Claim
122 words
An apparatus for analyzing communication lines, comprising: a primary processor; a dependent processor for receiving analog signals from the communications lines to be analyzed, digitally processing the received analog signals, and sending other analog signals to the communciations lines; and a digital information bus connecting said dependent processor to said primary processor, wherein said primary processor provides instructions to said dependent processor over the digital information bus, for controlling the manner in which the dependent processor processes analog signals, wherein said dependent processor provides data to said primary processor over the digital information bus, and wherein the primary processor performs overflow calculations using the data received from the dependent processor to increase the speed of the functions performed by said dependent processor."
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |