US4841366A
Expired / Lapsed
US
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Cyclic noise reducing apparatus
Assignee: NEC Home Electronics Ltd
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Filing: 1987-03-31
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Granted: 1989-06-20
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Expires: 2007-03-31
Abstract
Abstract A cyclic noise reducing apparatus for reducing noise in video signals by positively feeding back an output video signal which has been delayed through a field memory circuit for storing and selectively delaying video signals by a field (n lines) or by a field plus one line (n+1 lines) and cyclically adding the output video signal to an input video signal. The delay time is selected using a delay time switch for switching during a vertical scanning period the delay time of the signal positively fed back alternately between n and n+1 line periods. Also, the video signal may be alternately delayed by n or n+1 lines by suspending the writing and reading of data to and from the field memory circuit for one line period during the vertical blanking period of each frame.
Inventors
- 👤 Toshiyuki Katagiri
- 👤 Kazuhisa Marukado
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:07
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21; H04N5/76; H04N5/91; H04N5/911
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
105 words
A noise reducing apparatus comprising: means for delaying an input video signal by n lines for a first field and by n+1 lines for a second field to obtain a delayed video signal; means for cyclically adding said delayed video signal for each field to a subsequent signal of said input video signal to obtain an output video signal having reduced noise; and means for causing the delay of said first and second fields to be equal to a delay period of a frame delay to avoid half line shifting of said input video signal, said delay period corresponding to a delay of 2n+1 lines.
Claim 2
Dependent Claim
105 words
A noise reducing apparatus comprising: means for delaying an input video signal by n lines for a first field and by n+1 lines for a second field to obtain a delayed video signal; means for cyclically adding said delayed video signal for each field to a subsequent signal of said input video signal to obtain an output video signal having reduced noise; and means for causing the delay of said first and second fields to be equal to a delay period of a frame delay to avoid half line shifting of said input video signal, said delay period corresponding to a delay of 2n+1 lines.
Claim 3
Dependent Claim
19 words
An apparatus in accordance with claim 1, wherein said first field is odd and said second field is even.
Claim 4
Dependent Claim
64 words
An apparatus in accordance with claim 1, wherein said delaying means comprises a field memory circuit for delaying by n lines said input video signal to provide a field delayed video signal and a line memory circuit connected in series with said field memory circuit for delaying said field delayed video signal by one line to provide a field and line delayed video signal.
Claim 5
Dependent Claim
79 words
An apparatus in accordance with claim 3, wherein said delay causing means comprises a switching means connected to an output of said field memory circuit and to an output of said line memory circuit, respectively, said switching means alternatively connecting the output of said field memory circuit and the output of said line memory circuit which results in the output of said delayed video signal to said adding means during the vertical scanning period of said input video signal.
Claim 6
Dependent Claim
57 words
An apparatus in accordance with claim 4, wherein said delay causing means further comprises a control circuit coupled to said switching means for connecting the output of said field memory circuit to said adding means for said first field and for connecting the output of said line memory circuit to said adding means for said second field.
Claim 7
Independent Claim
83 words
An apparatus in accordance with clam 1, wherein said adding means comprises first and second serially connected subtractors, the difference between said subsequent input video signal and said delayed video signal being determined by said first subtractor, said difference then being attenuated by an attenuating means and applied as a first input to said second subtractor, the second input of second subtractor receiving said subsequent input video signal, and the output of said second subtractor representing said output video signal having reduced noise.
Claim 8
Independent Claim
83 words
An apparatus in accordance with clam 1, wherein said adding means comprises first and second serially connected subtractors, the difference between said subsequent input video signal and said delayed video signal being determined by said first subtractor, said difference then being attenuated by an attenuating means and applied as a first input to said second subtractor, the second input of second subtractor receiving said subsequent input video signal, and the output of said second subtractor representing said output video signal having reduced noise.
Claim 9
Dependent Claim
91 words
An apparatus in accordance with claim 1, wherein said delay causing means comprises: a field memory circuit for storing n lines of said input video signal; a vertical synchronizing separator responsive to said input video signal; a 1/2 divider for dividing the output of said vertical synchronizing separator; and memory access control means responsive to the output of said divider for suspending storing of said input video signal and outputting of said delayed video signal to and from said field memory circuit for one line period during a vertical blanking period.
Claim 10
Dependent Claim
84 words
An apparatus in accordance with claim 7, wherein said adding means comprises first and second serially connected subtractors, the difference between said another input video signal and said delayed video signal being determined by said first subtractor, said difference then being attenuated by an attenuating means and applied as a first input to said second subtractor, the second input of said second subtractor receiving said another input video signal, and the output of said second subtractor representing an output video signal having reduced noise.
Claim 11
Dependent Claim
93 words
A noise reducing apparatus comprising: means for delaying an input video signal by 262 lines for a first field and by 263 lines for a second field; means for cyclically adding a delayed video signal for each field to a subsequent signal of said input video signal to obtain an output video signal with reduced noise; and means for causing the delay of said first and second fields to be equal to a 525 line delay period of a frame delay to avoid half-line shifting of said input video signal for each field.
Claim 12
Dependent Claim
93 words
A noise reducing apparatus comprising: means for delaying an input video signal by 262 lines for a first field and by 263 lines for a second field; means for cyclically adding a delayed video signal for each field to a subsequent signal of said input video signal to obtain an output video signal with reduced noise; and means for causing the delay of said first and second fields to be equal to a 525 line delay period of a frame delay to avoid half-line shifting of said input video signal for each field.
Claim 13
Dependent Claim
92 words
A noise reducing apparatus comprising: means for delaying an input video signal by 262 lines for a first field and by 263 lines for a second field; means for cyclically adding a delayed video signal for each of said first and second fields to a subsequent signal of said input video signal to reduce noise; and means for switching the delay time of said delayed video signal between 262 and 263 lines during a vertical scanning period of said input video signal to avoid half line shifting of said input video signal.
Claim 14
Dependent Claim
92 words
A noise reducing apparatus comprising: means for delaying an input video signal by 262 lines for a first field and by 263 lines for a second field; means for cyclically adding a delayed video signal for each of said first and second fields to a subsequent signal of said input video signal to reduce noise; and means for switching the delay time of said delayed video signal between 262 and 263 lines during a vertical scanning period of said input video signal to avoid half line shifting of said input video signal.
Claim 15
Dependent Claim
108 words
An apparatus in accordance with claim 10, wherein said delaying means comprises a field memory circuit for delaying said input video signal 262 lines to provide a field delayed video signal and a line memory circuit connected in series with said field memory circuit for delaying said field delayed video signal by one line, said switching means being connected to an output of said field memory circuit and to an output of said line memory circuit, respectively, said switching means alternately switching between the output of said field memory circuit and the output of said line memory circuit during the vertical scanning period of said input video signal.
Claim 16
Dependent Claim
103 words
A noise reducing apparatus for reducing noise in video signals comprising: means for temporarily storing an input video signal so as to delay said input video signal by 262 lines to obtain a delayed video signal; means for cyclically adding said delayed video signal to a subsequent signal of said input video signal to obtain an output video signal with reduced noise; and means for suspending the writing and reading of data to and from said storing means for one line period during a vertical blanking period within a frame period to avoid half-line shifting of said input video signal for each field.
Claim 17
Dependent Claim
103 words
A noise reducing apparatus for reducing noise in video signals comprising: means for temporarily storing an input video signal so as to delay said input video signal by 262 lines to obtain a delayed video signal; means for cyclically adding said delayed video signal to a subsequent signal of said input video signal to obtain an output video signal with reduced noise; and means for suspending the writing and reading of data to and from said storing means for one line period during a vertical blanking period within a frame period to avoid half-line shifting of said input video signal for each field.
Claim 18
Dependent Claim
47 words
An apparatus in accordance with claim 12, wherein said data written to the storing and delaying means from the previous field is supplied to said adding means during said one line period during the vertical blanking period in which the writing and reading of data are suspended.
References Cited (Backward Citations)
US4291333A
Cited
US4434438A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |