US4841300A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error correction encoder/decoder
Assignee: Mitsubishi Electric Corp
•
Filing: 1987-06-17
•
Granted: 1989-06-20
•
Expires: 2007-06-17
Abstract
Abstract A separate operational section for determining the degree of a polynomial is provided to increase the process speed in determining both error locator and evaluator polynomials. When a received word is decoded based on the error location found, the received word is stored in a memory and corrected and output through the designation of the address. The formula ##EQU1## is derived from the error locator equation ##EQU2## and the value of which satisfies σ(α)=0 is determined to increase the process speed. The decoder and the encoder share part of the hardware to make the system compact.
Inventors
- 👤 Hideo Yoshida
- 👤 Tohru Inoue
- 👤 Atsuhiro Yamagishi
- 👤 Yoshiaki Oda
- 👤 Minoru Ozaki
- 👤 Toshihisa Nishijima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:22
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; H03M13/151; H03M13/033
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
167 words
An error correction encoder/decoder system comprising: a memory for storing a received coded word; a finite field logic circuit for deriving an error locator polynomial and an error evaluator polynomial from said received word, said finite field logic circuit including; arithmetic and logic means for determining degrees of both of said polynomials, said arithmetic and logic means having a memory for storing intermediate data in calculating both of said polynomials; Galois logic means responsive to said degrees to solve both of said polynomials for making correction of an error; and program means for controlling said Galois logic means and said arithmetic and logic means; a syndrome/Chien search computation circuit for determining a syndrome and an error location from the results output from said finite field logic circuit; and an address generation circuit arranged in a form of subtraction type counter circuit and responsive to said error location to generate an address in said memory so that the received word at said address may be fetched and corrected.
Claim 2
Dependent Claim
167 words
An error correction encoder/decoder system comprising: a memory for storing a received coded word; a finite field logic circuit for deriving an error locator polynomial and an error evaluator polynomial from said received word, said finite field logic circuit including; arithmetic and logic means for determining degrees of both of said polynomials, said arithmetic and logic means having a memory for storing intermediate data in calculating both of said polynomials; Galois logic means responsive to said degrees to solve both of said polynomials for making correction of an error; and program means for controlling said Galois logic means and said arithmetic and logic means; a syndrome/Chien search computation circuit for determining a syndrome and an error location from the results output from said finite field logic circuit; and an address generation circuit arranged in a form of subtraction type counter circuit and responsive to said error location to generate an address in said memory so that the received word at said address may be fetched and corrected.
Claim 3
Dependent Claim
23 words
An error correction encoder/decoder system according to claim 1, wherein said Galois logic means has three logic registers and two general purpose memories.
Claim 4
Dependent Claim
36 words
An error correction encoder/decoder system according to claim 1, wherein said Galois logic means determines an error location α i and an error pattern ei without normalizing said locator polynomial σ(z)=K.σ0(z) and said evaluator polynomial η(z)=K.η0(z).
Claim 5
Dependent Claim
22 words
An error correction encoder/decoder system according to claim 1, wherein said Galois logic means has a square circuit in a Galois field.
Claim 6
Dependent Claim
39 words
An error correction encoder/decoder system according to claim 1, wherein said arithmetic and logic means with memory having a degree latch circuit for inhibiting any writing on said memory when a predetermined flag is established in a predetermined interval.
Claim 7
Dependent Claim
40 words
An error correction encoder/decoder system according to claim 1, wherein said memory of said arithmetic and logic means has a degree latch circuit for inhibiting any writing on said memory when a predetermined flag is established in a predetermined interval.
Claim 8
Dependent Claim
127 words
An error correction encoder/decoder system according to claim 1, wherein said Galois logic means has a first general purpose memory and a second general purpose memory, and said arithmetic and logic means has a memory for storing the degree of a polynomial; said first and second general purpose memories being arranged so that the data input from said first general purpose memory may be input from said second general purpose memory in the next operation, and the data input from said second general purpose memory may be input from said first general purpose memory in the next operation and that said memory of said arithmetic and logic means may exchange the data assignments between a first address and a second address for operation without any data transfer.
Claim 9
Dependent Claim
78 words
An error correction encoder/decoder system according to claim 1, wherein said syndrome/Chien search computation circuit for determining an error location from both of said polynomials comprises: an adder for calculating ##EQU36## for said error locator polynomial ##EQU37## where α is an element in the Galois field, i an error location, and t the number of errors corrected; and a decision circuit for deciding whether said equation ##EQU38## satisfies zero thereby to determine an element α which satisfies σ(α)=0.
Claim 10
Dependent Claim
81 words
An error correction encoder/decoder system according to claim 1, wherein said syndrome/Chien search computation circuit comprises: a first memory for storing predetermined canstants; a multiplying circuit for multiplying a syndrome output from said syndrome computation means with constants read in succession from said first memory; and a summing circuit for summing in succession the multiplication results from said multiplying circuit to give the sum thereof so as to output a check symbol for the information input to said syndrome computation means.
References Cited (Backward Citations)
US4162480A
Cited
US4142174A
Cited
US4389636A
Cited
US4580162A
Cited
US4567594A
Cited
US4605921A
Cited
US4649541A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |