Solid-state imaging device having high-speed shutter function

Claim 2

A solid-state imaging device having a highspeed shutter function, comprising: a photosensitive section for storing charges corresponding to an amount of received light and a period of time during which the light is received; a vertical transfer section to which the storage charges in said photosensitive section are simultaneously transferred in response to a field shift pulse, said vertical transfer section vertically transferring the transferred charges in units of lines and at a high speed; first field memory means, having a one-field storage capacity for storing charges transferred from said vertical transfer section; second field memory means, having a one-field storage capacity for storing charges transferred from said vertical transfer section; transfer means for alternately transferring, in units of lines, the charges transferred from said vertical transfer section to said first and second field memory means; read means for reading out the charges stored in said first field memory means and reading out the charges stored in said second field memory means; and a horizontal transfer section for horizontally transferring, in units of lines, the charges read out by said read means.

Claim 3

The solid-state imaging device according to claim 1, wherein the number of vertical pixels in each of said first and second field memory means is 1/2 that of vertical pixels in said photosensitive section.

Claim 4

The solid-state imaging device according to claim 1, wherein said transfer means includes gate means arranged between said vertical transfer section and said first field memory means, and between said vertical transfer section and said second field memory means, and control means for controlling an enabled/disabled state of said gate means.

Claim 5

The solid-state imaging device according to claim 3, wherein said control means includes driver means for generating the field shift pulse and drive pulses for driving said vertical transfer section to transfer the transferred charges to said gate means, in units of lines and at a high speed, said driver means being arranged to generate control pulses for causing said gate means to transfer the charges, which are transferred from said vertical transfer section in units of lines, to said first and second field memory means, and alternately supply the control pulses to said gate means between said vertical transfer section and said first field memory means, and said gate means between said vertical transfer section and said second field memory means.

Claim 6

The solid-state imaging device according to claim 1, wherein said read means alternately reads out the charges from said first and second field memory means.

Claim 7

The solid-state imaging device according to claim 5, wherein said read means comprises: first read means, for reading out the charges from said first field memory means and reading out the charges from said second field memory means; second read means, for alternately reading out the charges from said first and second field memory means; and read control means for selectively operating said first and second read means.

Claim 8

The solid-state imaging device according to claim 5, wherein said read means includes gate means arranged between said first field memory means and said horizontal transfer section, and between said second field memory means and said horizontal transfer section, and control means for controlling an enabled/disabled state of said gate means.

Claim 9

The solid-state imaging device according to claim 7, wherein said control means includes driver means for generating the field shift pulse, said driver means being arranged to generate control pulses for causing said gate means to transfer the charges from said first and second field memory means to said horizontal transfer section, and said driver means being arranged to (a) supply the control pulses to said gate means arranged between said first field memory means and said horizontal transfer section, and then supply the control pulses to said gate means arranged between said second field memory means and said horizontal transfer section when the charges are read out from said first field memory means, and then the charges are read out from said second field memory means, and (b) alternately supply the control pulses to said gate means between said first field memory means and said horizontal transfer section, and to said gate means between said second field memory means and said horizontal transfer section, when the charges are alternately read out from said first and second memory means.

Claim 10

The solid-state imaging device according to claim 1, wherein said transfer means transfers the charges, which are transferred in units of lines from said vertical transfer section, to said first field memory means until said first field memory means is filled, and thereafter transfers the charges to said second field memory means.

Claim 11

The solid-state imaging device according to claim 9, wherein said transfer means comprises: first transfer means, for transferring the charges to said first field memory means until said first field memory means is filled, thereafter transferring the charges to said second field memory means; second transfer means, for alternately transferring the charges to said first and second field memory means; and transfer control means for selectively operating said first and second transfer means.

Claim 12

The solid-state imaging device according to claim 9, wherein said transfer means includes gate means between said vertical transfer section and said first field memory means, and between said vertical transfer section and said second field memory means, and control means for controlling a enabled/disabled state of said gate means.

Claim 13

The solid-state imaging device according to claim 11, wherein said control means includes driver means for generating the field shift pulse and drive pulses for driving said vertical transfer section to transfer the transferred charges to said gate means, in units of lines and at a high speed, said driver means being arranged to generate control pulses for causing said gate means to transfer the charges, which are transferred in units of lines from said vertical transfer section, to said first and second field memory means, and said driver means being arranged to (a) supply the control pulses to said gate means arranged between said vertical transfer section and said first field memory means, and then supply the control pulses to said gate means arranged between said vertical transfer section and said second field memory means, when the charges are transferred to said first field memory means, until said first field memory means is filled, and thereafter transfer the charges to said second field memory means, and (b) alternately supply the control pulses to said gate means between said vertical transfer section and said first field memory means, and to said gate means between said vertical transfer section said second field memory means when the charges are alternately transferred to said first and second memory means.