US4839713A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Package structure for semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1988-02-17
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Granted: 1989-06-13
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Expires: 2008-02-17
Abstract
Abstract A package structure comprising a metallic cap having a bottom wall to which the bottom surface of the semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding the semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting the lead conductors thereon through an electrically insulating material. The electrical connection means is disposed between the metallic cap flange and the lead conductor for establishing an electrical connection therebetween. The electrical connection means may comprise an electrically conductive projection formed on the flange of the metal cap, extending through a notch in the insulating material and electrically connected to the lead conductor. The electrical connection means may be an electrically conductive bonding material filled within a cavity defined by an opening in the flange of the metal cap, a through hole in the insulating material and a connecting pad of the lead conductor.
Inventors
- 👤 Yasuhiro Teraoka
- 👤 Tetsuya Ueda
- 👤 Hideya Yagoura
- 👤 Haruo Shimamoto
- 👤 Shigeyuki Nango
- 👤 Toshinobu Banjo
- 👤 Hiroshi Seki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:26
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/701; H10W70/00; H10W70/40; H10W70/453; H10W72/071; H10W72/077; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W76/40; H10W76/42; H10W76/47
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
194 words
A package structure for a semiconductor device to be manufactured by the TAB method and having a semiconductor chip having a first and a second electrode on the first and second major surfaces of the semiconductor chip, respectively, and lead conductors electrically connected to the electrodes, said package structure comprising: a metallic cap having a bottom wall to which a bottom surface of a semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding a semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting lead conductors of the chip through an electrically insulating material; and electrical connection means disposed between said flange of said metallic cap connected to the second electrode of the seimconductor chip and at least one of the lead conductors for connection to the second electrode and for establishing an electrical connection between said flange and at least one of the lead conductors and including an electrically conductive projection integrally disposed on said flange of said metal cap, extending through a notch in said insulating material, and electrically connected to the lead conductor.
Claim 2
Dependent Claim
194 words
A package structure for a semiconductor device to be manufactured by the TAB method and having a semiconductor chip having a first and a second electrode on the first and second major surfaces of the semiconductor chip, respectively, and lead conductors electrically connected to the electrodes, said package structure comprising: a metallic cap having a bottom wall to which a bottom surface of a semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding a semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting lead conductors of the chip through an electrically insulating material; and electrical connection means disposed between said flange of said metallic cap connected to the second electrode of the seimconductor chip and at least one of the lead conductors for connection to the second electrode and for establishing an electrical connection between said flange and at least one of the lead conductors and including an electrically conductive projection integrally disposed on said flange of said metal cap, extending through a notch in said insulating material, and electrically connected to the lead conductor.
Claim 3
Dependent Claim
37 words
A package structure for a semiconductor device as claimed in claim 1 comprising a wiring pattern electrically connected to the lead conductors and to said metallic cap and an electrically insulating substrate mechanically supporting said wiring pattern.
Claim 4
Dependent Claim
201 words
A package structure for a semiconductor device to be manufactured by the TAB method and having a semiconductor chip having a first and a second electrode on the first and second major surfaces of the semiconductor chip, respectively, and lead conductors electrically connected to the electrodes, said package structure comprising: a metallic cap having a bottom wall to which a bottom surface of a semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding a semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting lead conductors of the chip through an electrically insulating material; and electrical connection means disposed between said flange of said metallic cap connected to the second electrode of the semiconductor chip and at least one of the lead conductors for connection to the second electrode and for establishing an electrical connection between said flange and at least one of the lead conductors and including an electrically conductive bonding material disposed within a cavity defined by an opening in said flange of said metal cap, a through hole in said insulating material, and a connecting pad of the lead conductor.
Claim 5
Dependent Claim
201 words
A package structure for a semiconductor device to be manufactured by the TAB method and having a semiconductor chip having a first and a second electrode on the first and second major surfaces of the semiconductor chip, respectively, and lead conductors electrically connected to the electrodes, said package structure comprising: a metallic cap having a bottom wall to which a bottom surface of a semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding a semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting lead conductors of the chip through an electrically insulating material; and electrical connection means disposed between said flange of said metallic cap connected to the second electrode of the semiconductor chip and at least one of the lead conductors for connection to the second electrode and for establishing an electrical connection between said flange and at least one of the lead conductors and including an electrically conductive bonding material disposed within a cavity defined by an opening in said flange of said metal cap, a through hole in said insulating material, and a connecting pad of the lead conductor.
Claim 6
Dependent Claim
37 words
A package structure for a semiconductor device as claimed in claim 3 comprising a wiring pattern electrically connected to the lead conductors and to said metallic cap and an electrically insulating substrate mechanically supporting said wire pattern.
References Cited (Backward Citations)
US4330790A
Cited
US4649415A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |