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US4838993A
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Method of fabricating MOS field effect transistor
Assignee: Seiko Instruments Inc
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Filing: 1987-12-03
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Granted: 1989-06-13
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Expires: 2007-12-03
Abstract
Abstract A novel MOS field effect transistor which operates at high speed and with low power consumption has impurity doped source and drain regions deposited at 850° C. or less by molecular layer epitaxial growth method. The molecular layer epitaxial growth is concurrently carried out with the control of impurity doping concentration so that the layers epitaxially deposited has a lightly doped region and a heavily doped region. Since the thickness of the growth layer can be controlled with a degree of accuracy on the order of an atom layer and thermal diffusions can remarkably be reduced by the low deposition temperature, an overlap of a gate over each of the source and drain regions can be reduced to 500 Å or less.
Inventors
- 👤 Kenji Aoki
- 👤 Masafumi Shimbo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:19
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/60; H10D30/601; H10D30/608; H10D62/01; H10D62/021; H10D62/60; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
150 words
A process for fabricating a MOS field effect transistor comprising: a first step for thermally oxidizing a surface of a substrate of first semiconductor to form an oxide film, a second step for, after patterning, etching away said surface to form a gate insulated film, a source forming region and a drain forming region in said substrate, a third step for epitaxially depositing layers of second semiconductor in said source forming region and said drain forming region by applying an epitaxial growth method to form a source and a drain regions of second semiconductor having a lightly doped region and a heavily doped region therein, a fourth step for depositing a layer of polysilicon or other high melting point materials on said oxide film and said source and drain regions, and a fifth step for, after patterning, etching away said layer to form a gate on said gate insulated film.
Claim 2
Dependent Claim
150 words
A process for fabricating a MOS field effect transistor comprising: a first step for thermally oxidizing a surface of a substrate of first semiconductor to form an oxide film, a second step for, after patterning, etching away said surface to form a gate insulated film, a source forming region and a drain forming region in said substrate, a third step for epitaxially depositing layers of second semiconductor in said source forming region and said drain forming region by applying an epitaxial growth method to form a source and a drain regions of second semiconductor having a lightly doped region and a heavily doped region therein, a fourth step for depositing a layer of polysilicon or other high melting point materials on said oxide film and said source and drain regions, and a fifth step for, after patterning, etching away said layer to form a gate on said gate insulated film.
Claim 3
Dependent Claim
34 words
A process for fabricating a MOS field effect transistor according to claim 1; wherein said epitaxial growth method comprises a molecular beam epitaxial growth method carried out at temperatures of 850° C. or less.
Claim 4
Dependent Claim
38 words
A process for fabricating a MOS field effect transistor according to claim 1; wherein said lightly doped region and heavily doped region are provided by controlling the concentration of impurity concurrently with said epitaxial growth being carried out.
Claim 5
Dependent Claim
37 words
A process for fabricating a MOS field effect transistor according to claim 1; wherein said etching to form said source forming region and said drain forming region comprises an anisotropic etching such as a reactive ion etching.
References Cited (Backward Citations)
US4636269A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |