Abstract High speed interpolation machine for interpolating values in the transformation from one space to another. One important application is in the transformation from a transmission space to a display space for digital color television reproduction. The machine includes storage schemes for lookup table contents which permit parallel access to needed transformation coefficients during one clock cycle. The architecture results in a machine which can compute interpolation points quickly enough for real time digital television processing and requires a relatively small number of electronic components. The present invention will compute the interpolation function with approximately one eighth the memory requirements of a comparable high speed implementation. In one embodiment, the number of multiples is reduced and in another implementation, all of the multiplications can be eliminated. The transformation coefficients are stored in separate interpolation tables permitting parallel access.
An interpolation apparatus comprising: a total interpolation table comprising a plurality of interpolation subtables, each subtable storing a fraction of the total interpolation table; a plurality of address generation circuits for the interpolation subtables; a plurality of coefficient generation circuits; and circuitry to combine the coefficients and interpolation table values in parallel into a 3-dimensional interpolating function.
Claim 2
Dependent Claim
57 words
An interpolation apparatus comprising: a total interpolation table comprising a plurality of interpolation subtables, each subtable storing a fraction of the total interpolation table; a plurality of address generation circuits for the interpolation subtables; a plurality of coefficient generation circuits; and circuitry to combine the coefficients and interpolation table values in parallel into a 3-dimensional interpolating function.
Claim 3
Dependent Claim
42 words
The interpolation apparatus of claim 1 in which RAMs or ROMs are used to store the interpolation table and further including a plurality of coefficient RAMs or ROMs, one for each interpolation table, for storing the output of the coefficient generation circuits.
Claim 4
Dependent Claim
12 words
The apparatus of claim 1 for trilinear interpolation using eight interpolation tables.
Claim 5
Dependent Claim
12 words
The apparatus of claim 1 for linear interpolation using four interpolation tables.
Claim 6
Dependent Claim
34 words
The apparatus of claim 4 wherein the circuitry to combine the coefficients and interpolation table values generates tetrahedral subdivisions which alternate in adjacent subcubes of the interpolating range to yield a smooth interpolating function.
Claim 7
Dependent Claim
10 words
The apparatus of claim 4 involving only lookup table operations.
Claim 8
Dependent Claim
46 words
The apparatus of claim 1 in which the total interpolation table is represented by 2 M+N+O samples of the interpolating function, wherein 2 M 2 N 2 O are samples for the 3 dimensions of the domain variables where M, N, and O are arbitrary integers.