US4833537A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise reduction circuit for video signal having suitable nonlinear processing character
Assignee: Toshiba Corp
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Filing: 1987-12-22
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Granted: 1989-05-23
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Expires: 2007-12-22
Abstract
Abstract A noise reduction circuit stores the video signal of one frame as input through an A/D converter from a VTR main body, into a frame memory via a first subtracting circuit. A second subtracting circuit subtracts the delayed video signal delayed one frame, which is derived from said frame memory, from the video signal. The same outputs the subtraction result as a difference signal. The amplitude level of the video signal is detected by the detecting circuit. The nonlinear characteristic appropriate to the difference signal output from the subtracting circuit is selected by the level signal output from the detecting circuit. Subtracting circuit subtracts the noise component selected and extracted by the nonlinear processing circuit from the video signal, thereby to remove the noise component. The video signal with no noise component is applied through a D/A converter from the subtracting circuit, to a CRT display where it is visualized.
Inventors
- 👤 Motohiko Takeuchi
- 👤 Masaaki Kisou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:06
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/911; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
261 words
A noise reduction circuit for an input video signal, said circuit comprising: an A/D converter for converting an input video signal into a digital signal having an actual noise component; first subtracting circuit means for reducing the actual noise component contained in said input video signal from the digital signal of said A/D converter and for outputting the reduced signal; memory means for storing the output signal from said first subtracting circuit means, and for reading out said stored output signal with delay of a predetermined time of period; second subtracting circuit means for second subtracting the stored output signal read out of said memory means from the digital signal of said A/D converter, and for outputting the second subtraction result as a difference signal; detecting circuit means for detecting the digital signal from said A/D converter, said digital signal having a digital signal level, and said detecting circuit outputting a signal corresponding to the detected digital signal level; nonlinear processing circuit means with a plurality of predetermined nonlinear processing characteristic data corresponding to the signal from said detecting circuit means, said nonlinear processing circuit means extracting an extracted noise component from said difference signal by the signal from said detecting circuit means, and for outputting it to said first subtracting circuit means, said first subtracting circuit means reducing the actual noise component contained in said input video signal by subtracting the extracted noise component from the digital signal of said A/D converter; and a D/A converter for converting reduced signal from said first subtracting circuit means into an analog signal.
Claim 2
Dependent Claim
261 words
A noise reduction circuit for an input video signal, said circuit comprising: an A/D converter for converting an input video signal into a digital signal having an actual noise component; first subtracting circuit means for reducing the actual noise component contained in said input video signal from the digital signal of said A/D converter and for outputting the reduced signal; memory means for storing the output signal from said first subtracting circuit means, and for reading out said stored output signal with delay of a predetermined time of period; second subtracting circuit means for second subtracting the stored output signal read out of said memory means from the digital signal of said A/D converter, and for outputting the second subtraction result as a difference signal; detecting circuit means for detecting the digital signal from said A/D converter, said digital signal having a digital signal level, and said detecting circuit outputting a signal corresponding to the detected digital signal level; nonlinear processing circuit means with a plurality of predetermined nonlinear processing characteristic data corresponding to the signal from said detecting circuit means, said nonlinear processing circuit means extracting an extracted noise component from said difference signal by the signal from said detecting circuit means, and for outputting it to said first subtracting circuit means, said first subtracting circuit means reducing the actual noise component contained in said input video signal by subtracting the extracted noise component from the digital signal of said A/D converter; and a D/A converter for converting reduced signal from said first subtracting circuit means into an analog signal.
Claim 3
Dependent Claim
67 words
A circuit according to claim 1, wherein the output signal supplied to said memory means via the first subtracting circuit means for removing said actual noise component is the same as the digital signal of said A/D converter supplied to said second subtracting circuit means and said detecting circuit means in the case where said extracted noise component generated from said nonlinear processing circuit means is zero.
Claim 4
Dependent Claim
35 words
A circuit according to claim 2, wherein said detecting circuit means compares the digital signal generated from said A/D converter with a predetermined level, and generates a signal corresponding to the result of the comparison.
Claim 5
Dependent Claim
17 words
A circuit according to claim 3, wherein said detecting circuit means includes a plurality of predetermined levels.
Claim 6
Dependent Claim
20 words
A circuit according to claim 4, wherein the digital signal level of said detecting circuit means is an amplitude level.
Claim 7
Dependent Claim
52 words
A circuit according to claim 5, wherein said detecting circuit means compares the amplitude level of the digital signal from said A/D converter is compared with a slice level of upper and lower reference values of amplitude of said digital signal and outputs a signal corresponding to the result of the comparison.
Claim 8
Dependent Claim
33 words
A circuit according to claim 6, wherein said detecting circuit means includes a plurality of adders, and the output signal of said plurality of adders is output to said nonlinear processing circuit means.
Claim 9
Dependent Claim
36 words
A circuit according to claim 7, wherein said nonlinear processing circuit means includes a ROM, said ROM extracting said extracted noise component by selecting said signal from said detecting circuit means based on said difference signal.
Claim 10
Dependent Claim
68 words
A circuit according to claim 8, wherein said first subtracting circuit means includes an adder for adding said digital signal and said extracted noise component to produce said output signal, said second subtracting circuit means includes an inverter for inverting the data read out from said memory means, and an adder for adding the data applied through said inverter and said digital signal to provide said difference signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |