US4833397A
Expired / Lapsed
US
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Tester for verification of pulse widths in a digital system
Assignee: Unisys Corp
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Filing: 1987-04-06
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Granted: 1989-05-23
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Expires: 2007-04-06
Abstract
Abstract A tester-verifier apparatus operates to select a single one of a plurality of system clocks to verify that the clock width falls between accepted parameters. Secondarily, the apparatus selects representative clock signals for comparison with a reference clock to verify that the skew falls within accepted parameters. Additionally the apparatus can measure the exact time value of any pulse width or skew relationship to within 500 picoseconds (10 -12 ). Any selected system clock signal is split into two channels, one of which has a controlled delay time programmed by a microprocessor to develop minimum and maximum pulse parameters against which the selected clock signal is logically compared to see if the parameters are satisfied.
Inventors
- 👤 Frank McMurray, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:52
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937; G01R29/00; G01R29/02; G01R29/027; G01R29/0273; G01R31/31903; G01R31/31908; G01R31/3191; H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
An automated tester-verifier apparatus for selectively testing the pulsewidth of each one of a plurality of system clocks in a digital system comprising: (a) selection means for selecting a designated clock signal from a plurality of separate clock signals; (b) first and second channel means for respectively transmitting said designated clock signal, on said first channel means, directly to a result logic register means and, on said second channel means, via a programmable delay circuit means to said result logic register means; (c) microprocessor means for controlling said delay circuit means and for initially delaying said clock signal in said second channel means for a period, t a , representing the minimum allowable pulse width, and secondarily for a period, t x , representing the maximum allowable pulse width of said designated clock signal; (d) said result logic register means for logically signaling, to said microprocessor means, whether said designated clock signals fall within said t a and t x time periods.
Claim 2
Dependent Claim
162 words
An automated tester-verifier apparatus for selectively testing the pulsewidth of each one of a plurality of system clocks in a digital system comprising: (a) selection means for selecting a designated clock signal from a plurality of separate clock signals; (b) first and second channel means for respectively transmitting said designated clock signal, on said first channel means, directly to a result logic register means and, on said second channel means, via a programmable delay circuit means to said result logic register means; (c) microprocessor means for controlling said delay circuit means and for initially delaying said clock signal in said second channel means for a period, t a , representing the minimum allowable pulse width, and secondarily for a period, t x , representing the maximum allowable pulse width of said designated clock signal; (d) said result logic register means for logically signaling, to said microprocessor means, whether said designated clock signals fall within said t a and t x time periods.
Claim 3
Dependent Claim
78 words
The apparatus of claim 1 wherein said microprocessor means includes: (a) means to institute a series of cycles which provide an initial zero delay time period then a series of delay periods which are each incremented by 500 picoseconds for enabling said result logic register to sense the rising edge and the falling edge of said designated clock signal; (b) means to compute the actual value of the pulse width of said clock t d within 500 picoseconds.
Claim 4
Dependent Claim
23 words
The apparatus of claim 2 which includes: (a) display means connected to said microprocessor means for displaying said value of said pulse width.
Claim 5
Dependent Claim
46 words
The apparatus of claim 1 which includes: (a) calibration circuit means in said first channel means for nulling out any inherent circuit noise; (b) means in said microprocessor means for setting up a zero delay in said delay circuit to permit adjustment of said calibration means.
Claim 6
Independent Claim
162 words
An apparatus for selectively testing the pulse width of each one of a plurality of system clocks in a digital system comprising: (a) selection means for selecting a designated clock signal as a single source of signal clock information; (b) first channel means for transmitting said designated clock signal to the first input of a result logic register means; (c) second channel means for transmitting said designated clock signal to a second input of said result logic register means via a programmable delay circuit means; (d) microprocessor means for controlling and establishing a series of stepped delay time periods for delaying said clock signal in said second channel means and transmitting said clock signal, after said delay period, to a second input in said result logic register means. (e) said result logic register means for transmitting logical output signals to said microprocessor means to enable said microprocessor means to measure the actual value of the pulse width of said designated clock signal.
Claim 7
Independent Claim
162 words
An apparatus for selectively testing the pulse width of each one of a plurality of system clocks in a digital system comprising: (a) selection means for selecting a designated clock signal as a single source of signal clock information; (b) first channel means for transmitting said designated clock signal to the first input of a result logic register means; (c) second channel means for transmitting said designated clock signal to a second input of said result logic register means via a programmable delay circuit means; (d) microprocessor means for controlling and establishing a series of stepped delay time periods for delaying said clock signal in said second channel means and transmitting said clock signal, after said delay period, to a second input in said result logic register means. (e) said result logic register means for transmitting logical output signals to said microprocessor means to enable said microprocessor means to measure the actual value of the pulse width of said designated clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |