A driving signal generating unit having first and second voltage generators for selectively outputting a first voltage signal and a second voltage signal

Claim 2

A driving apparatus comprising a scanning driver circuit connected to scanning electrodes and a signal driver circuit connected to signal electrodes, said signal driver circuit comprising: a drive signal generating unit comprising: a first voltage output means associated with a first bus and second voltage output means associated with a second bus, each voltage output means comprising a positive voltage output circuit and a negative voltage output circuit; means for supplying a first pulse and a second pulse shifted in phase from the first pulse, wherein the first pulse induces an output from the negative voltage output circuit of the first voltage output means and the positive voltage output circuit of the second voltage output means, wherein the second pulse induces an output from positive voltage output circuit of the first voltage output means and the negative voltage output circuit of the second voltage output means to thereby supply a first voltage signal comprising a preceding negative voltage and subsequent positive voltage to the first bus from the first voltage output means and to supply a second voltage signal comprising a preceding positive voltage and a subsequent negative voltage to the second bus from the second voltage output means, the polarities of the voltages being defined with respect to the ground level; a switching circuit unit for selectively supplying the first or second voltage signal from the first or second bus to a signal electrode; and a switching signal generating unit for supplying a switching control signal to the switching circuit unit.

Claim 3

An apparatus according to claim 1, wherein said switching circuit unit comprises a transistor.

Claim 4

An apparatus according to claim 2, wherein the transistor in the switching circuit unit is a field effect transistor.

Claim 5

An apparatus according to claim 3, wherein said field effect transistor is a thin film transistor.

Claim 6

An apparatus according to claim 4, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 7

An apparatus according to claim 1, wherein said switching signal generating circuit includes a serial-parallel conversion circuit, a buffer circuit and an inversion circuit.

Claim 8

An apparatus according to claim 6, wherein said serial-parallel conversion circuit is a dynamic shift register.

Claim 9

An apparatus according to claim 6, wherein said switching signal generating unit comprises a field effect transistor.

Claim 10

An apparatus according to claim 8, wherein said field effect transistor is a thin film transistor.

Claim 11

An apparatus according to claim 9, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 12

A driving apparatus, comprising a signal driven circuit, for a display panel of the type comprising matrix electrodes formed by scanning electrodes and signal electrodes arranged to intersect with the scanning electrodes, wherein the contrast at each intersection of the scanning electrodes and the signal electrodes is discriminated depending on the direction of an electric field applied to th intersection, said scanning electrodes being connected to a scanning driver circuit and said signal electrodes being connected to a signal driver circuit; said apparatus comprising said signal drive circuit, and said signal driver circuit comprising: a drive signal generating unit further comprising: first voltage output means associated with a first bus and second voltage output means associated with a second bus, each voltage output means comprising a positive voltage output circuit and a negative voltage output circuit, means for supplying a first pulse and a second pulse shifted in phase from the first pulse, wherein the first pulse induces an output from the negative voltage output circuit of the first voltage output means and the positive voltage output circuit of the second voltage output means, wherein the second pulse induces an output from the positive voltage output circuit of the first voltage output means and the negative voltage output circuit of the second voltage output means, to thereby supply a first voltage signal comprising a preceding negative voltage and a subsequent positive voltage to the first bus from the first voltage output means and to thereby supply a second voltage signal comprising a preceding positive voltage and a subsequent negative voltage to tee second bus from the second voltage output means, the polarities of the voltages being defined with respect to the ground level; a switching circuit unit for selectively supplying the first or second voltage signal from the first or second bus to a signal electrode; and a switching signal generating unit for supplying a switching control signal to the switching circuit unit.

Claim 13

A driving apparatus, comprising a signal driven circuit, for a display panel of the type comprising matrix electrodes formed by scanning electrodes and signal electrodes arranged to intersect with the scanning electrodes, wherein the contrast at each intersection of the scanning electrodes and the signal electrodes is discriminated depending on the direction of an electric field applied to th intersection, said scanning electrodes being connected to a scanning driver circuit and said signal electrodes being connected to a signal driver circuit; said apparatus comprising said signal drive circuit, and said signal driver circuit comprising: a drive signal generating unit further comprising: first voltage output means associated with a first bus and second voltage output means associated with a second bus, each voltage output means comprising a positive voltage output circuit and a negative voltage output circuit, means for supplying a first pulse and a second pulse shifted in phase from the first pulse, wherein the first pulse induces an output from the negative voltage output circuit of the first voltage output means and the positive voltage output circuit of the second voltage output means, wherein the second pulse induces an output from the positive voltage output circuit of the first voltage output means and the negative voltage output circuit of the second voltage output means, to thereby supply a first voltage signal comprising a preceding negative voltage and a subsequent positive voltage to the first bus from the first voltage output means and to thereby supply a second voltage signal comprising a preceding positive voltage and a subsequent negative voltage to tee second bus from the second voltage output means, the polarities of the voltages being defined with respect to the ground level; a switching circuit unit for selectively supplying the first or second voltage signal from the first or second bus to a signal electrode; and a switching signal generating unit for supplying a switching control signal to the switching circuit unit.

Claim 14

An apparatus according to claim 11, which further comprises clock means for synchronizing said first and second voltage signals supplied from said signal driver circuit to the signal electrodes with a scanning selection signal supplied from said scanning driver circuit to a scanning electrode.

Claim 15

An apparatus according to claim 11, wherein the positive polarity voltage and the negative polarity voltage have the same amplitude.

Claim 16

An apparatus according to claim 11, wherein each of said first and second voltage signals comprise a voltage of a positive polarity, a voltage of a negative polarity and a voltage of the same level respectively with respect to a ground potential, and the first and second voltage signals are of mutually different phases.

Claim 17

An apparatus according to claim 14, wherein the positive polarity voltage and the negative polarity voltage have the same amplitude.

Claim 18

An apparatus according to claim 11, wherein said switching circuit unit comprises a transistor.

Claim 19

An apparatus according to claim 16, wherein the transistor in the switching circuit unit is a field effect transistor.

Claim 20

An apparatus according to claim 17, wherein said field effect transistor is a thin film transistor.

Claim 21

An apparatus according to claim 18, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 22

An apparatus according to claim 11, wherein said switching signal generating circuit includes a serial-parallel conversion circuit, a buffer circuit and an inversion circuit.

Claim 23

An apparatus according to claim 20, wherein said serial-parallel conversion circuit is a dynamic shift register.

Claim 24

An apparatus according to claim 1, wherein said switching signal generating unit comprises a field effect transistor.

Claim 25

An apparatus according to claim 22, wherein said field effect transistor is a thin film transistor.

Claim 26

An apparatus according to claim 23, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 27

An apparatus according to claim 1, wherein a ferroelectric liquid crystal is disposed at the intersections of the scanning electrodes and the signal electrodes.

Claim 28

An apparatus according to claim 25, wherein said ferroelectric liquid crystal is a chiral smectic liquid crystal.

Claim 29

An apparatus according to claim 26, wherein said chiral smectic liquid crystal is disposed in a layer thin enough to release the helical structure inherent to the chiral smectic liquid crystal in the absence of an electric field.

Claim 30

A driving apparatus comprising a scanning driver circuit connected to scanning electrodes and a signal driver circuit connected to signal electrodes, said signal driver circuit comprising: (1) a drive signal generating unit which includes a first signal generating circuit and a second signal generating circuit for generating a first voltage signal and a second voltage signal, respectively, comprising mutually different polarity waveforms at a corresponding phase; (2) a switching control signal generating unit including (a) a serial-parallel conversion circuit, and (b) a matrix circuit which includes a plurality of switching elements divided into a plurality of blocks, the switching elements in each block being commonly connected to a control line, the output signals from the serial-parallel conversion circuit being distributed to the respective blocks; and (3) a switching circuit unit for selectively supplying the first or second voltage signal to a signal electrode depending on a switching control signal supplied form the switching control signal generating unit.

Claim 31

A driving apparatus comprising a scanning driver circuit connected to scanning electrodes and a signal driver circuit connected to signal electrodes, said signal driver circuit comprising: (1) a drive signal generating unit which includes a first signal generating circuit and a second signal generating circuit for generating a first voltage signal and a second voltage signal, respectively, comprising mutually different polarity waveforms at a corresponding phase; (2) a switching control signal generating unit including (a) a serial-parallel conversion circuit, and (b) a matrix circuit which includes a plurality of switching elements divided into a plurality of blocks, the switching elements in each block being commonly connected to a control line, the output signals from the serial-parallel conversion circuit being distributed to the respective blocks; and (3) a switching circuit unit for selectively supplying the first or second voltage signal to a signal electrode depending on a switching control signal supplied form the switching control signal generating unit.

Claim 32

An apparatus according to claim 28, wherein said switching control signal generating unit includes (a) the serial-parallel conversion circuit, (b) the matrix circuit, and (c) a buffer circuit.

Claim 33

An apparatus according to claim 28, wherein said switching control signal generating unit includes (a) the serial-parallel conversion circuit, (b) the matrix circuit, (c) a buffer circuit, and (d) an inversion circuit.

Claim 34

An apparatus according to claim 29, wherein said serial-parallel conversion circuit comprises a dynamic shift register.

Claim 35

An apparatus according to claim 31, wherein said dynamic shift register comprises a field effect transistor.

Claim 36

An apparatus according to claim 32, wherein said field effect transistor is a thin film transistor.

Claim 37

An apparatus according to claim 33, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 38

An apparatus according to claim 28, wherein said switching elements respectively comprise a field effect transistor.

Claim 39

An apparatus according to claim 35, wherein said field effect transistor is a thin film transistor.

Claim 40

An apparatus according to claim 36, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 41

An apparatus according to claim 28, wherein said first and second voltage signals are supplied to their exclusive buses respectively from the drive signal generating unit.

Claim 42

A driving apparatus, comprising a signal driver circuit for a display panel of the type comprising matrix electrodes formed by scanning electrodes and signal electrodes arranged intersect with the scanning electrodes wherein a contrast at each intersection of the scanning electrodes and the signal electrodes is discriminated depending on the direction of an electric field applied to the intersection, said scanning electrodes being connected to a scanning driver circuit and said signal electrodes being connected to said signal driver circuit, said signal driver circuit comprising: (1) a drive signal generating unit which includes a first signal generating circuit and a second signal generating circuit for generating a first voltage signal and a second voltage signal, respectively, comprising mutually different polarity waveforms at a corresponding phase; (2) a switching control signal generating unit including (a) a serial-parallel conversion circuit, and (b) a matrix circuit which includes a plurality of switching elements divided into a plurality of blocks, the switching elements in each block being commonly connected to a control line, the output signals from the serial-parallel conversion circuit being distributed to the respective blocks; and (3) a switching circuit unit for selectively supplying the first or second voltage signal to a signal supplied from the switching control signal generating unit.

Claim 43

A driving apparatus, comprising a signal driver circuit for a display panel of the type comprising matrix electrodes formed by scanning electrodes and signal electrodes arranged intersect with the scanning electrodes wherein a contrast at each intersection of the scanning electrodes and the signal electrodes is discriminated depending on the direction of an electric field applied to the intersection, said scanning electrodes being connected to a scanning driver circuit and said signal electrodes being connected to said signal driver circuit, said signal driver circuit comprising: (1) a drive signal generating unit which includes a first signal generating circuit and a second signal generating circuit for generating a first voltage signal and a second voltage signal, respectively, comprising mutually different polarity waveforms at a corresponding phase; (2) a switching control signal generating unit including (a) a serial-parallel conversion circuit, and (b) a matrix circuit which includes a plurality of switching elements divided into a plurality of blocks, the switching elements in each block being commonly connected to a control line, the output signals from the serial-parallel conversion circuit being distributed to the respective blocks; and (3) a switching circuit unit for selectively supplying the first or second voltage signal to a signal supplied from the switching control signal generating unit.

Claim 44

An apparatus according to claim 39, which further comprises clock means for synchronizing said first and second voltage signals supplied from said signal driver circuit to the signal electrodes with a scanning selection signal supplied from said scanning driver circuit to a scanning electrode.

Claim 45

An apparatus according to claim 39, wherein each of said first and second voltage signals comprises a voltage of a positive polarity and a voltage of a negative polarity with respect to a ground potential, and the first and second voltage signals have mutually different phases.

Claim 46

An apparatus according to claim 41, wherein the positive polarity voltage and the negative polarity voltage have the same amplitude.

Claim 47

An apparatus according to claim 41, wherein said first and second voltage signals are of mutually opposite phases.

Claim 48

An apparatus according to claim 39, wherein each of said first and second voltage signals comprises a voltage of a positive polarity, a voltage of a negative polarity and a voltage of the same level respectively with respect to a ground potential, and the first and second voltage signals are of mutually different phases.

Claim 49

An apparatus according to claim 44, wherein the positive polarity voltage and the negative polarity voltage have the same amplitude.

Claim 50

An apparatus according to claim 39, wherein said switching control signal generating unit includes (a) the serial-parallel conversion circuit, (b) the matrix circuit, and (c) a buffer circuit.

Claim 51

An apparatus according to claim 39, wherein said switching control signal generating unit includes (a) the serial-parallel conversion circuit, (b) the matrix circuit, (c) a buffer circuit, and (d) an inversion circuit.

Claim 52

An apparatus according to claim 46, wherein said serial-parallel conversion circuit comprises a dynamic shift register.

Claim 53

An apparatus according to claim 48, wherein said dynamic shift register comprises a field effect transistor.

Claim 54

An apparatus according to claim 49, wherein said field effect transistor is a thin film transistor.

Claim 55

An apparatus according to claim 50, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 56

An apparatus according to claim 39, wherein said switching elements respectively comprise a field effect transistor.

Claim 57

An apparatus according to claim 52, wherein said field effect transistor is a thin film transistor.

Claim 58

An apparatus according to claim 53, wherein said thin film transistor comprises a semiconductor film of amorphous silicon, polysilicon, CdSe or ZnSe.

Claim 59

An apparatus according to claim 39, wherein a ferroelectric liquid crystal is disposed at the intersections of the scanning electrodes and the signal electrodes.

Claim 60

An apparatus according to claim 55, wherein said ferroelectric liquid crystal is a chiral smectic liquid crystal.

Claim 61

An apparatus according to claim 56, wherein said chiral smectic liquid crystal is disposed in a layer thin enough to release the helical structure inherent to the chiral smectic liquid crystal in the absence of an electric field.