Method and apparatus for measuring the resistance of the winding of a converter-fed single- or three phase machine during operation

Claim 3

The method for measuring the resistance of a winding recited in claim 1, further comprising controlling the variable setting angle so that an RMS current formed from the measured machine current is continuously associated with a corresponding setting angle, the d-c measuring current remaining constant.

Claim 4

The method for measuring the resistance of a winding recited in claim 1, further comprising controlling the variable setting angle so that the RMS current is inversely proportioned to the setting angle.

Claim 5

The method for measuring the resistance of a winding recited in claim 1, further comprising controlling the variable setting angle in dependence on the amplitude of an intermediate-link voltage fed to the converter coupled to the machine.

Claim 6

A circuit arrangement for measuring the resistance of a winding of a converter-fed single- or three-phase machine during operation by means of a d-c measuring current present as a d-c component of a phase current, comprising, means for delaying a firing instant of at least one commutating-up valve of a converter coupled to the machine by a predetermined variable setting angle thereby generating d-c measuring currents in phase currents of the machine, whereby the current conduction time of the commutating-up valve is shortened and the current conduction time of a valve commutating-down with the one commutating-up valve, is lengthened; first means for filtering at least one generated d-c measuring current from a measured phase current and second means for filtering a generated interlinked d-c measuring voltage from a measured terminal voltage of the single- or three-phase machine, where the measured terminal voltage comprises the phase voltages which contain a respective d-c component due to the valves which commutate up with delay; and means for determining the winding resistance from the interlinked d-c measuring voltage and the d-c measuring current by forming a quotient, further comprising a control unit having at least one shifting arrangement which shifts the firing instant of at least one valve of the converter in time; at least one shunt resistor being arranged in a connecting lead between the converter and the single- or three-phase machine so that it can be bridged, the resistor having terminals coupled to said first filtering means comprising a first low pass filter, the first low pass filter being coupled to a first input of said means for forming comprising quotient forming means, the quotient forming means having a second input connected to two terminals of the converter-fed single- or three-phase machine via said second filtering means comprising a second low pass.

Claim 7

A circuit arrangement for measuring the resistance of a winding of a converter-fed single- or three-phase machine during operation by means of a d-c measuring current present as a d-c component of a phase current, comprising, means for delaying a firing instant of at least one commutating-up valve of a converter coupled to the machine by a predetermined variable setting angle thereby generating d-c measuring currents in phase currents of the machine, whereby the current conduction time of the commutating-up valve is shortened and the current conduction time of a valve commutating-down with the one commutating-up valve, is lengthened; first means for filtering at least one generated d-c measuring current from a measured phase current and second means for filtering a generated interlinked d-c measuring voltage from a measured terminal voltage of the single- or three-phase machine, where the measured terminal voltage comprises the phase voltages which contain a respective d-c component due to the valves which commutate up with delay; and means for determining the winding resistance from the interlinked d-c measuring voltage and the d-c measuring current by forming a quotient, further comprising a control unit having at least one shifting arrangement which shifts the firing instant of at least one valve of the converter in time; at least one shunt resistor being arranged in a connecting lead between the converter and the single- or three-phase machine so that it can be bridged, the resistor having terminals coupled to said first filtering means comprising a first low pass filter, the first low pass filter being coupled to a first input of said means for forming comprising quotient forming means, the quotient forming means having a second input connected to two terminals of the converter-fed single- or three-phase machine via said second filtering means comprising a second low pass.

Claim 8

The circuit arrangement recited in claim 5, wherein the shifting arrangement comprises two RS flip-flops, two backward counters and an AND gate, where the undelayed firing-instant signal is fed to a set input of the first RS flip-flop, of which the noninverting output is tied to an enable input of the first backward counter and an inverting output of the RS flip-flop is connected to an input of the first backward counter, which accomplishes presetting of the first backward counter, a clock input of the first backward counter being connected to a clock generator; an inverting output of the first backward counter being tied to a set input of the second RS flip-flop, the noninverting output of the second RS flip-flop being connected to an enable input of the second backward counter and an inverting output of the second flip-flop being connected to an input of the second backward counter which accomplishes the presetting of the second backward counter, a clock input of the second backward counter being connected to the clock generator; an inverting output of the second backward counter being tied to respective reset inputs of the two RS flip-flops; the clock signals of the clock generator being fed to a first input of the AND gate, a second input of which is tied to the noninverting output of the second RS flip-flop, a delayed pulse train for an up-commutating valve being present at the output of the AND gate.

Claim 9

The circuit arrangement recited in claim 6, wherein each of the first and second backward counters comprise a programmable backward counter.

Claim 10

The circuit arrangement recited in claim 5, wherein the resistor terminals of the shunt resistor are tied to an RMS value converter having an output connected to a characteristic-curve generator, the characteristic-curve generator being connected to the presetting inputs of the first programmable backward counter.

Claim 11

The circuit arrangement recited in claim 8, wherein the characteristic-curve generator comprises a programmable memory.