US4829019A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment
Assignee: Texas Instruments Inc
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Filing: 1987-05-12
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Granted: 1989-05-09
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Expires: 2007-05-12
Abstract
Abstract A method of forming semiconductor devices wherein a gap is formed beneath the field oxide between the channel stop implant and source/drain regions in the moat or active element region to prevent or minimize encroachment of channel stop impurity toward the source/drain regions to form spurious pn junctions and/or reduce the active element region.
Inventors
- 👤 Allan T. Mitchell
- 👤 Howard L. Tigelaar
- 👤 Bert R. Riemenschneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:32
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/22; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
92 words
A method of fabricating semiconductor devices, comprising the steps of: (a) providing a semiconductor substrate having a first patterned mask thereon; (b) implanting a channel stop impurity into said substrate in the unmasked regions thereof; (b.1) providing a second patterned mask over a portion of said first patterned mask; (c) removing a portion of said first patterned mask not masked by said second patterned mask; (d) forming a field oxide over the unmasked regions of said substrate, and (e) forming active semiconductor regions in the regions masked by said first patterned mask.
Claim 2
Independent Claim
92 words
A method of fabricating semiconductor devices, comprising the steps of: (a) providing a semiconductor substrate having a first patterned mask thereon; (b) implanting a channel stop impurity into said substrate in the unmasked regions thereof; (b.1) providing a second patterned mask over a portion of said first patterned mask; (c) removing a portion of said first patterned mask not masked by said second patterned mask; (d) forming a field oxide over the unmasked regions of said substrate, and (e) forming active semiconductor regions in the regions masked by said first patterned mask.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein said first mask is formed of silicon nitride and said second mask is formed of photoresist.
Claim 4
Dependent Claim
31 words
The method of claim 1 wherein step (e) comprises forming a source/drain region in said substrate in the region thereof beneath said first mask of conductivity type opposite to said impurity.
Claim 5
Dependent Claim
31 words
The method of claim 2 wherein step (e) comprises forming a source/drain region in said substrate in the region thereof beneath said first mask of conductivity type opposite to said impurity.
References Cited (Backward Citations)
JPS56137650A
Cited
JPS5723219A
Cited
US4442591A
Cited
JPS59165434A
Cited
JPS59224141A
Cited
JPS61100944A
Cited
USH204H
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-08 | 1992-11-07 | 1993-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-08 | 1996-11-07 | 1997-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-08 | 2000-11-07 | 2001-05-09 | $7700.00 | Window Closed / Lapsed |