US4827400A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Segment descriptor present bit recycle and detect logic for a memory management unit
Assignee: Bull HN Information Systems Inc
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Filing: 1986-04-07
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Granted: 1989-05-02
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Expires: 2006-04-07
Abstract
Abstract A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.
Inventors
- 👤 Llewelyn S. Dunwell
- 👤 Richard P. Brown
- 👤 Arthur Peters
- 👤 John L. Curley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:49
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
A data processing system includes apparatus for translating logical addresses to physical addresses, said apparatus comprising: main memory means for storing information organized in segments, said segments being stored in locations specified by said physical addresses; central processing unit means for generating said logical addresses, each corresponding to one of said physical addresses; memory management unit means coupled to said central processor means and including first memory means for storing segment descriptors in m locations specified by said logical addresses, and including second memory means for storing m bits in n locations specified by said logical addresses, each of said m bits indicating if a corresponding segment descriptor is stored in a location specified by a logical address, each of said descriptors including a physical address, said memory management unit further including means for clearing said second memory means in response to a clear signal from said central processor unit means and a sequence of n logical addresses from said central processor unit means to said second memory means; said central processor unit means being coupled to said main memory means and said memory management unit means for receiving a physical address for transfer to said main memory means in response to a corresponding logical address if one of said m bits stored in one of said n locations specified by said logical address indicates that said segment descriptor including said physical address is stored in said first memory means wherein m is greater than n.
Claim 2
Dependent Claim
246 words
A data processing system includes apparatus for translating logical addresses to physical addresses, said apparatus comprising: main memory means for storing information organized in segments, said segments being stored in locations specified by said physical addresses; central processing unit means for generating said logical addresses, each corresponding to one of said physical addresses; memory management unit means coupled to said central processor means and including first memory means for storing segment descriptors in m locations specified by said logical addresses, and including second memory means for storing m bits in n locations specified by said logical addresses, each of said m bits indicating if a corresponding segment descriptor is stored in a location specified by a logical address, each of said descriptors including a physical address, said memory management unit further including means for clearing said second memory means in response to a clear signal from said central processor unit means and a sequence of n logical addresses from said central processor unit means to said second memory means; said central processor unit means being coupled to said main memory means and said memory management unit means for receiving a physical address for transfer to said main memory means in response to a corresponding logical address if one of said m bits stored in one of said n locations specified by said logical address indicates that said segment descriptor including said physical address is stored in said first memory means wherein m is greater than n.
Claim 3
Dependent Claim
194 words
The apparatus of claim 1 wherein said memory management unit comprises: said first memory means having m locations for storing each of said segment descriptors describing the location of the first word of each of said segments at locations specified by said logical addresses, each of said logical addresses having a first portion and a second portion; and said second memory means coupled to said first memory means and having said m bits stored in said n locations, said each of said m bits corresponding to one of said m locations in said first memory means, one of said m bits in a first state indicating that said corresponding segment descriptor is present in said first memory means, and said one of said m bits in a second state indicating that said corresponding segment descriptor is not present in said first memory means, said second memory means being responsive to said first portion of one of said logical addresses for generating a first m bit signal representative of said one of said m bits and m/n minus one first bit signals representative of the state of the respective remaining bits of a selected location.
Claim 4
Dependent Claim
99 words
The apparatus of claim 2 wherein said memory management unit further comprises: multiplexer means coupled to said second memory means and responsive to said second portion of said logical address, for selecting said first m bit signal in a first state and generating a present signal in a first state indicating that said one of said segment descriptors is present in said first memory means, and selecting said first m bit signal in a second state and generating said present signal in a second state indicating that said corresponding segment descriptor is not present in said first memory means.
Claim 5
Dependent Claim
80 words
The apparatus of claim 3 wherein said memory management unit further comprises: first register means coupled to said multiplexer means and responsive to said present signal in said second state for generating a first signal indicating that said one of said segment descriptors is not stored in said first memory means, said central processor unit means being responsive to said first signal for writing said one of said segment descriptors in said first memory means at said logical address location.
Claim 6
Dependent Claim
249 words
The apparatus of claim 4 wherein said memory management unit further comprises: second register means coupled to said first register means for storing said first m bit signal and said m/n minus one first bit signals and responsive to said first signal for generating a second m bit signal and m/n minus one second bit signals respectively; decoder means coupled to said first register means and responsive to said second portion of said one of said logical addresses and said first signal for generating a position signal in a second state corresponding to said second m bit signal and m/n minus one position signals each in a first state corresponding to said m/n minus one second bit signals respectively; and gating means coupled to said decoder means, said second register means and said second memory means and responsive to said second m bit signal in a second state and said position signal in said second state for generating a third m bit signal in a first state, and responsive to said m/n minus one position signals, each in said first state and corresponding ones of said m/n minus one second bit signals for generating m/n minus one third bit signals, said second memory means being responsive to said third m bit signal in said first state for writing said m bit in said first state, and responsive to said m/n minus one third bit signal for rewriting in their original state the respective remaining bits of said selected location.
Claim 7
Dependent Claim
15 words
The apparatus of claim 5 wherein m equals 128 and n equals 16 and m/n=8.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-01 | 1992-10-31 | 1993-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-01 | 1996-10-31 | 1997-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-01 | 2000-10-31 | 2001-05-02 | $7700.00 | Window Closed / Lapsed |