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US4827200A Expired / Lapsed US ⏱️ 0.0 years remaining

Velocity control unit of detecting head

Assignee: Mitsubishi Electric Corp
•
Filing: 1988-04-01
•
Granted: 1989-05-02
•
Expires: 2008-04-01
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Abstract

Abstract A velocity control unit of a detecting head consists of a differentiation circuit for differentiating a reference velocity signal and feeding it via an analog switch to a first-order lag circuit which generates a feedforward signal. The analog switch is controlled by a constant velocity/deceleration detecting circuit so that it may be turned on in the constant velocity/deceleration period of the head.

Inventors

  • 👤 Shirou Ogura
  • 👤 Shigemasa Yoshida

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 19:53
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/416; G05B2219/00; G05B2219/30; G05B2219/41; G05B2219/41437

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 192 words
An apparatus for controlling the velocity of a detecting head for performing a seek operation by quickly moving said detecting head from a present position to a target track, which comprises: a reference velocity signal generator for generating a reference velocity signal corresponding to the number of tracks between said target track and said present position of said detecting head; a velocity converter for generating an actual velocity signal proportional to a measured velocity of said detecting head; a differential circuit for receiving said reference velocity signal and said actual velocity signal and generating a velocity error signal; a constant velocity/deceleration period detecting circuit for receiving said velocity error signal and generating a logic signal indicative of a constant velocity/deceleration period in said seek operation; a feedforward signal generator in response to said logic signal to differentiate said reference velocity signal, forming a first-order lag feedforward signal; a sum amplifier for receiving said velocity error signal and said feedforward signal and generating a driving signal; and a power amplifier for receiving said driving signal and supplying an electric current for driving a voice coil motor to which said detecting head is secured.
Claim 2
Independent Claim 192 words
An apparatus for controlling the velocity of a detecting head for performing a seek operation by quickly moving said detecting head from a present position to a target track, which comprises: a reference velocity signal generator for generating a reference velocity signal corresponding to the number of tracks between said target track and said present position of said detecting head; a velocity converter for generating an actual velocity signal proportional to a measured velocity of said detecting head; a differential circuit for receiving said reference velocity signal and said actual velocity signal and generating a velocity error signal; a constant velocity/deceleration period detecting circuit for receiving said velocity error signal and generating a logic signal indicative of a constant velocity/deceleration period in said seek operation; a feedforward signal generator in response to said logic signal to differentiate said reference velocity signal, forming a first-order lag feedforward signal; a sum amplifier for receiving said velocity error signal and said feedforward signal and generating a driving signal; and a power amplifier for receiving said driving signal and supplying an electric current for driving a voice coil motor to which said detecting head is secured.
Claim 3
Dependent Claim 48 words
The apparatus of claim 1, wherein said feedforward signal generator comprises: a differentiation circuit for receiving said reference velocity signal and generating a differentiation signal; an analog switch in response to said logic signal to open or close; and a first-order lag circuit for lagging said differentiation signal.
Claim 4
Dependent Claim 22 words
The apparatus of claim 1, wherein said differentiation circuit and said first-order lag circuit are made up of a dc differential amplifier.
Claim 5
Dependent Claim 18 words
The apparatus of claim 1, wherein said analog switch is made up of a field effect solid-state switch.
Claim 6
Dependent Claim 70 words
The apparatus of claim 1, wherein said constant velocity/deceleration period detecting circuit comprises: a delay circuit for delaying a seek command; a pair of comparators for sensing inversion of a sign of said velocity error signal; and a flip-flop for receiving an output from said delay circuit at its reset terminal and an output from said comparators at its set terminal and generating a logic signal at its output terminal.

References Cited (Backward Citations)

US4200827A Cited
US4133011A Cited
US4337428A Cited
US4469996A Cited
US4535372A Cited
US4594622A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-05-01 1992-10-31 1993-05-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-05-01 1996-10-31 1997-05-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-05-01 2000-10-31 2001-05-02 $7700.00 Window Closed / Lapsed

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