US4825389A
Expired / Lapsed
US
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Print data editing circuit in serial printer
Assignee: Toshiba Corp
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Filing: 1986-06-04
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Granted: 1989-04-25
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Expires: 2006-06-04
Abstract
Abstract In a print data editing circuit in a serial printer of the invention, print data signals for odd pins (P1, P3, P9, P11, P17, P19) and other odd pins (P5, P7, P13, P15, P21, P23) in print data supplied from a buffer RAM are sequentially shifted and stored in first and second registers in response to a first write signal. Similarly, print data signals for even pins (P2, P4, P10, P12, P18, P20) and other even pins (P6, P8, P14, P16, P22, P24) are sequentially shifted and stored in third and fourth registers in response to a second write signal. The print data signals from the first through fourth registers are respectively latched by first through fourth buffer registers in response to an interrupt signal from a timer. The data signals are simultaneously output from the first through fourth buffer registers and supplied to a pin drive circuit.
Inventors
- 👤 Hideo Masaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:53
CPC Classifications
G; G06; G06K; G06K15/00; G06K15/02; G06K15/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
515 words
A print data editing circuit in a serial printer having printing pins arranged in two staggered columns, and driver means for driving the respective pins, comprising: print data memory means for storing the print data; write signal generating means for generating first and second write signals; first register means for storing, in response to a first occurrence of the first write signal, odd bit print data comprising 2 N-1 -bits (N being a positive integer of one or more) among 2 N -bits of print data stored in said print data memory means at address "m" (m being a positive integer), and for storing, in response to second and third occurrences of the first write signals, odd bit print data comprising 2 N-1 -bits among 2 N -bits of data stored in said print data memory means at addresses "m+1" and "m+2", respectively; second register means, connected to said first register means, for storing, in response to the second occurrence of the first write signal, odd bit print data comprising said 2 N-1 -bits among 2 N -bits of data at address "m", and for storing, in response to the third occurrence of the first write signal, odd bit print data comprising said 2 N-1 -bits among 2 N -bits of data at address "m+1"; and third register means, connected to said second register means, for storing, in response to the third occurrence of the first write signal, odd bit print data comprising 2 N-1 -bits among said 2 N -bits of print data at address "m", thereby setting the odd bit print data comprising 2 N -bits to be supplied to said driving means, in said first through third register means; fourth register means for storing, in response to a first occurrence of the second write signal, even bit print data comprising 2 N-1 -bits among 2 N -bits of print data stored in said print data memory means at address "m+a" (each of m and a being a positive integer), and for storing, in response to second and third occurrences of the second write signals, even bit print data comprising 2 N-1 -bits among 2 N -bits of print data stored in said print data memory means at addresses "m+a+1" and "m+a+2", respectively; fifth register means, connected to said fourth register means, for storing, in response to the second occurrence of the second write signal, odd bit print data comprising said 2 N-1 -bits among 2 N -bits of print data at address "m+a", and for storing, in response to the third occurrence of the second write signal, even bit print data comprising said 2 N-1 -bits among 2 N -bits of print data at address "m+a+1"; and sixth register means, connected to said fifth register means, for storing, in response to the third occurrence of the second write signal, even bit print data comprising said 2 N-1 -bits among 2 N -bit print data at address "m+a", thereby setting the even bit print data comprising 2 N -bits to be supplied to said driving means, in said fourth to sixth register means.
Claim 2
Dependent Claim
515 words
A print data editing circuit in a serial printer having printing pins arranged in two staggered columns, and driver means for driving the respective pins, comprising: print data memory means for storing the print data; write signal generating means for generating first and second write signals; first register means for storing, in response to a first occurrence of the first write signal, odd bit print data comprising 2 N-1 -bits (N being a positive integer of one or more) among 2 N -bits of print data stored in said print data memory means at address "m" (m being a positive integer), and for storing, in response to second and third occurrences of the first write signals, odd bit print data comprising 2 N-1 -bits among 2 N -bits of data stored in said print data memory means at addresses "m+1" and "m+2", respectively; second register means, connected to said first register means, for storing, in response to the second occurrence of the first write signal, odd bit print data comprising said 2 N-1 -bits among 2 N -bits of data at address "m", and for storing, in response to the third occurrence of the first write signal, odd bit print data comprising said 2 N-1 -bits among 2 N -bits of data at address "m+1"; and third register means, connected to said second register means, for storing, in response to the third occurrence of the first write signal, odd bit print data comprising 2 N-1 -bits among said 2 N -bits of print data at address "m", thereby setting the odd bit print data comprising 2 N -bits to be supplied to said driving means, in said first through third register means; fourth register means for storing, in response to a first occurrence of the second write signal, even bit print data comprising 2 N-1 -bits among 2 N -bits of print data stored in said print data memory means at address "m+a" (each of m and a being a positive integer), and for storing, in response to second and third occurrences of the second write signals, even bit print data comprising 2 N-1 -bits among 2 N -bits of print data stored in said print data memory means at addresses "m+a+1" and "m+a+2", respectively; fifth register means, connected to said fourth register means, for storing, in response to the second occurrence of the second write signal, odd bit print data comprising said 2 N-1 -bits among 2 N -bits of print data at address "m+a", and for storing, in response to the third occurrence of the second write signal, even bit print data comprising said 2 N-1 -bits among 2 N -bits of print data at address "m+a+1"; and sixth register means, connected to said fifth register means, for storing, in response to the third occurrence of the second write signal, even bit print data comprising said 2 N-1 -bits among 2 N -bit print data at address "m+a", thereby setting the even bit print data comprising 2 N -bits to be supplied to said driving means, in said fourth to sixth register means.
Claim 3
Dependent Claim
331 words
A print data editing circuit in a serial printer having printing pins arranged in two staggered columns, and driver means for driving the respective pins, comprising: print data memory means for storing the print data; write signal generating means for generating first and second write signals; first register means for storing, in response to first, second and third occurrence of a first write signal, odd bit print data comprising the most significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bits of print data stored in said print data memory means at addresses "m", "m+1", and "m+2" (m being a positive integer), respectively; second register means for storing, in response to the first, second and third occurrences of the first write signal, odd bit print data comprising the least significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bit print data stored in said print data memory means at addresses "m", "m+1", and "m+2" (m being a positive integer), respectively; third register means for storing, in response to the first, second and third occurrences of a second write signal, even bit print data comprising the most significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bits of print data stored in said print data memory means at addresses "m+a", "m+a+1", and "m+a+2" (both "m" and "a" being a positive integer), respectively; and fourth register means for storing, in response to the first, second and third occurrences of the second write signal, even bit print data comprising the least significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bits of print data stored in said print data memory means at addresses "m+a", "m+a+1", and "m+a+2" respectively, thereby setting, in said first through fourth register means, the odd and even bit print data each comprising 2 N-2 -bits to be supplied to said driving means.
Claim 4
Dependent Claim
331 words
A print data editing circuit in a serial printer having printing pins arranged in two staggered columns, and driver means for driving the respective pins, comprising: print data memory means for storing the print data; write signal generating means for generating first and second write signals; first register means for storing, in response to first, second and third occurrence of a first write signal, odd bit print data comprising the most significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bits of print data stored in said print data memory means at addresses "m", "m+1", and "m+2" (m being a positive integer), respectively; second register means for storing, in response to the first, second and third occurrences of the first write signal, odd bit print data comprising the least significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bit print data stored in said print data memory means at addresses "m", "m+1", and "m+2" (m being a positive integer), respectively; third register means for storing, in response to the first, second and third occurrences of a second write signal, even bit print data comprising the most significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bits of print data stored in said print data memory means at addresses "m+a", "m+a+1", and "m+a+2" (both "m" and "a" being a positive integer), respectively; and fourth register means for storing, in response to the first, second and third occurrences of the second write signal, even bit print data comprising the least significant 2 N-2 -bits (N being a positive integer of one or more), among 2 N -bits of print data stored in said print data memory means at addresses "m+a", "m+a+1", and "m+a+2" respectively, thereby setting, in said first through fourth register means, the odd and even bit print data each comprising 2 N-2 -bits to be supplied to said driving means.
Claim 5
Dependent Claim
38 words
A print data editing circuit according to claim 2, further comprising first through fourth latch means, connected to said first through fourth register means, for storing the print data output from said first through fourth register means, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |