US4825174A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetric integrated amplifier with controlled DC offset voltage
Assignee: Nokia Bell Labs
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Filing: 1988-06-20
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Granted: 1989-04-25
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Expires: 2008-06-20
Abstract
Abstract A symmetric integrated FET amplifier is disclosed which exhibits a DC offset voltage that is insensitive to power supply variations, as well as variations in the threshold voltages of the FETs forming the amplifier. These variations are known to be most prevalent in InP-based FET amplifier arrangements. The symmetry is achieved by using a pair of impedance matching elements in the input stage of the amplifier to essentially match the impedance of the input FET and its load element, and a matching buffer FET and diode level shifting arrangement are used to match similar elements present in the output branch of the amplifier structure. The impedance matching elements, as well as the level shifting diodes, may all be formed with FET structures to minimize fabrication problems. In accordance with the symmetric arrangement of the present invention, the output DC offset voltage will be maintained at zero volts, regardless of the variations noted above. A multistage symmetric amplifier may then be formed simply by directly connecting a number of single stage symmetric amplifiers together in series.
Inventors
- 👤 George P. Vella-Coleiro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:31
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/04; H03F3/16; H03F1/00; H03F1/30; H03F1/306; H03F1/307; H03F1/309
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
275 words
A symmetric integrated FET amplifier comprising an input FET including a gate, source and drain, responsive to an applied input voltage signal; input load means coupled between the drain of said input FET and a first power supply source; first impedance matching means connected to the source of said input FET, said first impedance matching means comprising an impedance value essentially the impedance of said input load means; second impedance matching means connected between said first impedance matching means and a second power supply source, said second impedance matching means comprising an impedance value essentially the impedance of said input FET; a first buffer FET including a gate, source and drain, the gate being coupled to the drain of said input FET, the drain being coupled to said first power supply source; first voltage level shifting means coupled between the source of said first buffer FET and the amplifier output, said first voltage level shifting means for supplying a predetermined DC voltage drop to the signal appearing at the gate of said first buffer FET; a second buffer FET including a gate, source and drain, the gate being coupled to the connection between said first and second impedance matching means and the source being coupled to the first voltage level shifting means at the amplifier output, said second buffer FET being essentially identical in size to said first buffer FET; and second voltage level shifting means coupled between the drain of said second buffer FET and said second power supply source, said second voltage level shifting means for supplying said predetermined DC voltage to the signal appearing at the gate of said second buffer FET.
Claim 2
Dependent Claim
275 words
A symmetric integrated FET amplifier comprising an input FET including a gate, source and drain, responsive to an applied input voltage signal; input load means coupled between the drain of said input FET and a first power supply source; first impedance matching means connected to the source of said input FET, said first impedance matching means comprising an impedance value essentially the impedance of said input load means; second impedance matching means connected between said first impedance matching means and a second power supply source, said second impedance matching means comprising an impedance value essentially the impedance of said input FET; a first buffer FET including a gate, source and drain, the gate being coupled to the drain of said input FET, the drain being coupled to said first power supply source; first voltage level shifting means coupled between the source of said first buffer FET and the amplifier output, said first voltage level shifting means for supplying a predetermined DC voltage drop to the signal appearing at the gate of said first buffer FET; a second buffer FET including a gate, source and drain, the gate being coupled to the connection between said first and second impedance matching means and the source being coupled to the first voltage level shifting means at the amplifier output, said second buffer FET being essentially identical in size to said first buffer FET; and second voltage level shifting means coupled between the drain of said second buffer FET and said second power supply source, said second voltage level shifting means for supplying said predetermined DC voltage to the signal appearing at the gate of said second buffer FET.
Claim 3
Dependent Claim
19 words
A symmetric integrated FET amplifier as defined by claim 1 wherein the input load means comprises a resistive element.
Claim 4
Dependent Claim
56 words
A symmetric integrated FET amplifier as defined by claim 1 wherein the input load means is an active load comprising an FET including gate, drain and source, the drain of the load FET coupled to the first power supply source, the gate and the source connected together and coupled to the drain of the input FET.
Claim 5
Dependent Claim
23 words
A symmetric integrated FET amplifier as defined by claim 1 wherein the first and second impedance matching means each comprise a resistor element.
Claim 6
Dependent Claim
102 words
A symmetric integrated FET amplifier as defined by claim 1 wherein the first impedance matching means comprises an FET including gate, drain and source, the drain of the first impedance matching FET coupled to the source of the input FET, the gate and the source connected together; and the second impedance matching means comprises an FET including gate, drain and source, the drain of the second impedance matching FET coupled to the connected gate and source of said first impedance matching FET, the gate and source of said second impedance matching FET connected together and coupled to the second power supply source.
Claim 7
Dependent Claim
42 words
A symmetric integrated FET amplifier as defined by claim 1 wherein the first and second voltage level shifting means each comprise a series connection of N diode elements (N≧1), each diode element capable of providing a specific voltage drop (V diode ).
Claim 8
Dependent Claim
50 words
A symmetric integrated FET amplifier as defined by claim 6 wherein the first and second voltage level shifting means each comprise a plurality of M diode elements (M>1), wherein the predetermined DC voltage drop provided by said first and second voltage level shifting means will be essentially M*V diode .
Claim 9
Dependent Claim
21 words
A symmetric integrated FET amplifier as defined by claims 6 or 7 wherein each diode element comprises a source-drain connected FET.
Claim 10
Dependent Claim
290 words
A multistage integrated FET amplifier comprising a plurality of N separate stages directly connected in series, each separate amplifier stage comprising an input FET including a gate, source and drain, responsive to an applied input voltage signal; input load means coupled between the drain of said input FET and a first power supply source; first impedance matching means connected to the source of said input FET, said first impedance matching means comprising an impedance value essentially the impedance of said input load means; second impedance matching means connected between said first impedance matching means and a second power supply source, said second impedance matching means comprising an impedance value essentially the impedance of said input FET; a first buffer FET including a gate, source and drain, the gate being coupled to the drain of said input FET, the drain being coupled to said first power supply source; first voltage level shifting means coupled between the source of said first buffer FET and the amplifier output, said first voltage level shifting means for supplying a predetermined DC voltage drop to the signal appearing at the gate of said first buffer FET; a second buffer FET including a gate, source and drain, the gate being coupled to the connection between said first and second impedance matching means and the source being coupled to the first voltage level shifting means at the amplifier output, said second buffer FET being essentially identical in size to said first buffer FET; and second voltage level shifting means coupled between the drain of said second buffer FET and said second power supply source, said second voltage level shifting means for supplying said predetermined DC voltage to the signal appearing at the gate of said second buffer FET.
Claim 11
Dependent Claim
290 words
A multistage integrated FET amplifier comprising a plurality of N separate stages directly connected in series, each separate amplifier stage comprising an input FET including a gate, source and drain, responsive to an applied input voltage signal; input load means coupled between the drain of said input FET and a first power supply source; first impedance matching means connected to the source of said input FET, said first impedance matching means comprising an impedance value essentially the impedance of said input load means; second impedance matching means connected between said first impedance matching means and a second power supply source, said second impedance matching means comprising an impedance value essentially the impedance of said input FET; a first buffer FET including a gate, source and drain, the gate being coupled to the drain of said input FET, the drain being coupled to said first power supply source; first voltage level shifting means coupled between the source of said first buffer FET and the amplifier output, said first voltage level shifting means for supplying a predetermined DC voltage drop to the signal appearing at the gate of said first buffer FET; a second buffer FET including a gate, source and drain, the gate being coupled to the connection between said first and second impedance matching means and the source being coupled to the first voltage level shifting means at the amplifier output, said second buffer FET being essentially identical in size to said first buffer FET; and second voltage level shifting means coupled between the drain of said second buffer FET and said second power supply source, said second voltage level shifting means for supplying said predetermined DC voltage to the signal appearing at the gate of said second buffer FET.
Claim 12
Dependent Claim
19 words
A multistage integrated FET amplifier as defined by claim 9 wherein the input load means comprises a resistive element.
Claim 13
Dependent Claim
56 words
A multistage integrated FET amplifier as defined by claim 9 wherein the input load means is an active load comprising an FET including gate, drain and source, the drain of the load FET coupled to the first power supply source, the gate and the source connected together and coupled to the drain of the input FET.
Claim 14
Dependent Claim
23 words
A multistage integrated FET amplifier as defined by claim 9 wherein the first and second impedance matching means each comprise a resistor element.
Claim 15
Dependent Claim
102 words
A multistage integrated FET amplifier as defined by claim 9 wherein the first impedance matching means comprises an FET including gate, drain and source, the drain of the first impedance matching FET coupled to the source of the input FET, the gate and the source connected together; and the second impedance matching means comprises an FET including gate, drain and source, the drain of the second impedance matching FET coupled to the connected gate and source of said first impedance matching FET, the gate and source of said second impedance matching FET connected together and coupled to the second power supply source.
Claim 16
Dependent Claim
42 words
A multistage integrated FET amplifier as defined by claim 9 wherein the first and second voltage level shifting means each comprise a series connection of N diode elements (N>=1), each diode element capable of providing a specific voltage drop (V diode ).
Claim 17
Dependent Claim
50 words
A multistage integrated FET amplifier as defined by claim 14 wherein the first and second voltage level shifting means each comprise a plurality of M diode elements (M>1), wherein the predetermined DC voltage drop provided by said first and second voltage level shifting means will be essentially M*V diode .
Claim 18
Dependent Claim
21 words
A multistage integrated FET amplifier as defined by claims 14 or 15 wherein each diode element comprises a source-drain connected FET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |