Method and circuit apparatus for checking the authorization of access to a signal processing system

Claim 3

The method of authorizing access as recited in claim 1 of a peripheral unit, in particular, a control station of a signal processing system to data stored in said signal processing system, characterized in that, prior to obtaining access to such data, the access authorization is checked by means of a code number, allocated to a respective control station (BS), by means of the identification data freely selectable for the respective control station, and by means of a keyword entered in the signal processing system (SVS) for the respective control station.

Claim 4

The method of authorizing access as recited in claim 1 for activating control sequences concerning operation of a signal processing system from a control station of the signal processing system, characterized in that, prior to an activation of the control sequences, access authorization concerning the respective control station (BS) is checked by means of a code number allocated to the control station, by means of the freely selectable identification data for the respective control station, and by means of a keyword entered in the signal processing system (SVS) for the respective control station.

Claim 5

A method as recited in claim 1, further characterized in that, in addition to the code number allocated to the respective peripheral unit and identification data, a system code number designated for the signal processing system (SVS) can be integrated in the derivation of the keyword and the checking method of the access authorization.

Claim 6

A method as recited in claim 1 for identifying calling and/or called subscriber terminals (TS1 through TS4) of a respective packet data switching center integrated in the switched connections which run through packet data switching centers (e.g., PV2) of a packet switching network, characterized in that, in placing into operation a switched through communications channel, a keyword is entered in the packet data switching center for each subscriber terminal communicating with the packet data switching center via a communications channel, the keyword in the packet data switching center being derived from the specified freely selectable identification data and the calling number allocated to the respective subscriber terminal such that, in the course of setting up a connection, the calling number allocated to the respective subscriber terminal is transmitted along with the respective identification data in a packet initiating said setup; and the transmitted calling number and associated identification data are always combined with the keyword allocated to the respective subscriber terminal for the purpose of subscriber terminal identification.

Claim 7

The method as recited in claim 5, further characterized in that the process of establishing a connection only proceeds in the event of a correct identification of the respective calling and/or called subscriber terminal.

Claim 8

The method as recited in claim 5, further characterized in that, with subscriber terminals which are connected via a PBX (NST) with the packet data switching center (PV2), the operator of said PBX selects separate identification data for each of said subscriber terminals.

Claim 9

The method as defined in claim 5 further characterized in that a packet for initiating the establishment of a connection also transmits information signals requesting specific services, which, after an identification of the respective subscriber terminal, are accepted as parameters for the specific services.

Claim 10

Circuit apparatus for implementing a method of authorizing access to a signal processing system characterized in that the signal processing system (SVS) has a memory configuration (SWS) with a number of storage cells corresponding to a number of peripheral units seeking access to the signal processing system, the memory configuration for the purpose of storing keywords allocated to the peripheral units (TE, BS) seeking access such that a first register (KR) is provided for buffering a code number transmitted by one of the peripheral units, and a second register (IIR) is provided for buffering the identification data pertaining to the respective code number, a combinatorial circuit (VS) being linked to said registers (KR, IIR) and the memory configuration (SWS), the combinatorial circuit for combining the code numbers transmitted by the two registers and the identification data pertaining thereto with the keywords corresponding to the respective code numbers.

Claim 11

Circuit apparatus for implementing a method of authorizing access to a signal processing system characterized in that the signal processing system (SVS) has a memory configuration (SWS) with a number of storage cells corresponding to a number of peripheral units seeking access to the signal processing system, the memory configuration for the purpose of storing keywords allocated to the peripheral units (TE, BS) seeking access such that a first register (KR) is provided for buffering a code number transmitted by one of the peripheral units, and a second register (IIR) is provided for buffering the identification data pertaining to the respective code number, a combinatorial circuit (VS) being linked to said registers (KR, IIR) and the memory configuration (SWS), the combinatorial circuit for combining the code numbers transmitted by the two registers and the identification data pertaining thereto with the keywords corresponding to the respective code numbers.