US4819202A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Release process for an access-controlled user memory and apparatus for carrying out the process
Assignee: Siemens AG
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Filing: 1986-07-07
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Granted: 1989-04-04
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Expires: 2006-07-07
Abstract
Abstract A process for carrying out a release operation for a user memory includes releasing a user function in dependence on a preceding data comparison of externally entered data with reference data stored in a code memory, continuously changing the content of a control memory ahead of every release, and monitoring the change through a comparison of the initial control memory content with the changed control memory content and apparatus for carrying out the method.
Inventors
- 👤 Hartmut Schrenk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:18
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06; G06F; G06F21/00; G06F21/70; G06F21/71; G06F21/77; G06F21/78; G06F21/79; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/341; G07F7/1025; G07F7/1083; G11; G11C; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
182 words
Apparatus for carrying-out a validation operation for a chip card with a user memory, comprising a code memory for storing reference data; a comparator having an input connected to said code memory for receiving said reference data, and an input for receiving externally entered data and an output; a first logical gate having an input connected to said output of said comparator, an input for receiving a respective control signal from an address of said code memory and an output; a control memory having an output; a second logical gate having an input connected to said output of said control memory, an input receiving a control signal from a corresponding address of said control memory and an output; a first bistable circuit having in input connected to said output of said first logical gate and an output; a second bistable circuit having an input connected to said output of said second logical gate and an output; and a third logical gate having inputs respectively connected to said outputs of said first and second bistable circuits and said output of said control memory.
Claim 2
Dependent Claim
182 words
Apparatus for carrying-out a validation operation for a chip card with a user memory, comprising a code memory for storing reference data; a comparator having an input connected to said code memory for receiving said reference data, and an input for receiving externally entered data and an output; a first logical gate having an input connected to said output of said comparator, an input for receiving a respective control signal from an address of said code memory and an output; a control memory having an output; a second logical gate having an input connected to said output of said control memory, an input receiving a control signal from a corresponding address of said control memory and an output; a first bistable circuit having in input connected to said output of said first logical gate and an output; a second bistable circuit having an input connected to said output of said second logical gate and an output; and a third logical gate having inputs respectively connected to said outputs of said first and second bistable circuits and said output of said control memory.
Claim 3
Dependent Claim
29 words
Apparatus according to claim 1, wherein said logical gates are NOR gates, said first bistable circuit is a code flip-flop, and said second bistable circuit is a bit flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-03 | 1992-10-03 | 1993-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-03 | 1996-10-03 | 1997-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-03 | 2000-10-03 | 2001-04-04 | $7700.00 | Window Closed / Lapsed |