Multiple-precision Booth's recode multiplier

Claim 1

A binary multiplier circuit for multiplying a multiplier and a multiplicand to form a product, comprising: recode means for dividing said multiplier into a plurality of Booth sub-groups of three bits each; recode logic means for operating on said multiplicand, in accordance with the binary digits of said Booth sub-groups of said multiplier, to form an intermediate set of partial products according to the modified Booth's recode algorithm; intermediate partial product storage means for storing said partial products; and adder array means for combining said partial products to form said product, characterized in that: said multiplier circuit further includes multiple-precision means for dividing said multiplier into at least two intermediate multiplier sub-groups of binary digits, each of which is operated on by said recode means to form two sets of Booth recode sub-groups; said recode logic means includes at least two recode sub-units for operating on said multiplicand in parallel to form at least two sets of intermediate partial products, each set corresponding to a multiplier sub-group and each intermediate partial product of a set corresponding to a Booth recode sub-group; combining means, responsive to said multiplicand and said multiplier, and connected to said intermediate partial product storage means for combining intermediate partial products, within one of said sets of intermediate partial products, that attaches an additional term of each intermediate multiplier sub-group to said set of intermediate partial products, the value of which additional term depends in a predetermined manner on said multiplicand and on the most significant bit of said intermediate multiplier sub-group.