Application specific integrated circuit

Claim 2

A circuit for cooperation with serial data sending and receiving means which comprises: a terminal for data path connection with said means; register means for serially receiving data from, and for serially feeding data therein to, said terminal; means for storing data received in said register means; means for feeding data into said register means for subsequent feeding to said terminal; timing oscillator means for generating a shift clock signal for said register means for stepping the register means synchronously with said serially received data from said terminal and for stepping said register means at a predetermined rate when serially feeding data therein to said terminal; validating means detecting presence of start and stop bit data in predetermined locations in said register means defining a data phrase received at said terminal; means detecting command bit data in said data phrase; means responsive to simultaneous output of said validating means and to output of said command bit data detecting means for switching said means for storing data and said register means in accordance with said command bit data.

Claim 3

In a system comprising a pair of data handling stations linked by a data transmission path and comprising interrogation and data receiving means at one of said stations, means at the other station comprising: register means for serially receiving data from and for serially transmitting data in said register means to, said first station; means for storing data received in said register means; means for feeding data into said register means for subsequent transmission; timing oscillator means for providing timing functions for said second station means and for synchronizing data flow from, and data reception capability at, said first station means; said timing means generating a shift clock signal for said register means for stepping said register means synchronously with serially received data from said first station and for stepping said register means synchronously with the data reception capability at said first station; validating means detecting presence of start and stop bit data in predetermined locations in said register means defining a data phrase received from said first station; means detecting command bit data in said received phrase; and means responsive to simultaneous output of said validating means and to output of said command bit data detecting means for switching said means for storing data and said means for feeding data in accordance with said command bit data.

Claim 4

In a system comprising a pair of data handling stations linked by a data transmission path and comprising interrogation and data receiving means at one of said stations, means at the other station comprising: register means for serially receiving data from and for serially transmitting data in said register means to, said first station; means for storing data received in said register means; means for feeding data into said register means for subsequent transmission; timing oscillator means for providing timing functions for said second station means and for synchronizing data flow from, and data reception capability at, said first station means; said timing means generating a shift clock signal for said register means for stepping said register means synchronously with serially received data from said first station and for stepping said register means synchronously with the data reception capability at said first station; validating means detecting presence of start and stop bit data in predetermined locations in said register means defining a data phrase received from said first station; means detecting command bit data in said received phrase; and means responsive to simultaneous output of said validating means and to output of said command bit data detecting means for switching said means for storing data and said means for feeding data in accordance with said command bit data.

Claim 5

In a system defined in claim 2, input means at said second station for said data feeding means, said simultaneous responsive means actuating said feeding means and said input means.

Claim 6

In a system as defined in claim 2, further means at said second station responsive to said simultaneous responsive means for switching data path terminal means at said second station to provide an output terminal for data from said register means.

Claim 7

In a system defined in claim 2, said first station providing a data bit in said phrase for sequencing through a part of said register means by said shift clock signal, said bit thereby respectively interrogating individual inputs from said second station input means for feeding into respective stages of said register means.

Claim 8

In a system comprising a pair of data handling stations linked by a data transmission path and comprising interrogation and data receiving means at a first of said stations, means at the second of said stations comprising: register means for receiving serial data from said first station; latch means for storing data received in said register means; timing oscillator means for providing timing functions for said second station means and for synchronizing data flow from and data reception capability at, said first station; said timing means generating a shift clock signal for said register means for stepping said register means synchronously with a data bit stream received from said first station; validating means detecting presence of start and stop bit data defining said stream in predetermined locations in said register means; means detecting command bit data in said stream; means responsive to the output of said validating means and to detected command bit data for switching said latch means for storing data received in said register means; and output means responsive to said latch means for driving output devices at said second station.

Claim 9

In a system comprising a pair of data handling stations linked by a data transmission path and comprising interrogation and data receiving means at a first of said stations, means at the second of said stations comprising: register means for receiving serial data from said first station; latch means for storing data received in said register means; timing oscillator means for providing timing functions for said second station means and for synchronizing data flow from and data reception capability at, said first station; said timing means generating a shift clock signal for said register means for stepping said register means synchronously with a data bit stream received from said first station; validating means detecting presence of start and stop bit data defining said stream in predetermined locations in said register means; means detecting command bit data in said stream; means responsive to the output of said validating means and to detected command bit data for switching said latch means for storing data received in said register means; and output means responsive to said latch means for driving output devices at said second station.

Claim 10

In a system defined in claim 6, input means at said second station for loading said register means independently of input from said first station, and further means at said second station responsive to said validating means and detected command bit data received in said register means from said first station for actuating said register means to receive input from said second station input means.

Claim 11

In a system as defined in claim 6, second further means at said second station responsive to said validating means and detected command bit data in said data register means from said first station for condtioning said second station for transmitting data placed in said register means by said second station input means through said data path to said first station.

Claim 12

In a system defined in claim 6, said first station providing a data bit in said serial data for sequencing through a part of said register means by said shift clock signal, said bit thereby respectively interrogating individual inputs from said second station input means for loading into respective stages of said register means.

Claim 13

In a system defined in claim 6, selected latch means storing respective data bits received in said register means from said serial data for controlling respective analog switches at said second station; and individual sensor means connected to said respective analog switches for producing a timing pulse of duration corresponding to a value measured by the respective sensor, and means responsive to said validating means and detected command bit data for feeding said timing pulse as output to the first station.

Claim 14

In a system defined in claim 2, means sensitive to a voltage level in said data path and responsive to a shift in said level following a period at said level without change, comprising: bi-stable means first switched by said level shift and further switched by change back to said first mentioned level; second bi-stable means responsive to the first switching of the first mentioned bi-stable means; and delay means preventing reset of said second bi-stable during a predetermined period for all subsequent switching of said first bi-stable, switching of said second bi-stable generating a clock reset pulse for synchronizing timing functions provided by said timing oscillator means.

Claim 15

A circuit which comprises, a shift register, mode control means for said circuit for conditioning said shift register to a plurality of operating states, local data generating means, a terminal for receipt and transmission of serial data fed thereto, storage means for subsequent utilization of data received by said shift register from said terminal, said mode control means alternatively conditioning said shift register for receiving serial data from said terminal and for conditioning said shift register for receiving local data from said local data generating means, said mode control means also conditioning said shift register for feeding said local data therein serially to said terminal, and means responsive to chosen received serial data at said terminal for actuating said mode control means.

Claim 16

A circuit which comprises, a shift register, mode control means for said circuit for conditioning said shift register to a plurality of operating states, local data generating means, a terminal for receipt and transmission of serial data fed thereto, storage means for subsequent utilization of data received by said shift register from said terminal, said mode control means alternatively conditioning said shift register for receiving serial data from said terminal and for conditioning said shift register for receiving local data from said local data generating means, said mode control means also conditioning said shift register for feeding said local data therein serially to said terminal, and means responsive to chosen received serial data at said terminal for actuating said mode control means.

Claim 17

A circuit as defined in claim 12, serial data received from said terminal including a specific data bit, shift clock means for sequentially moving said data bit for actuating gate means for said local data generating means for sequentially feeding local generated data into respective chosen stages of said shift register.

Claim 18

A circuit as defined in claim 12, said local data generating means comprising charge responsive means for generating a pulse of duration dependent upon time from a chosen start point to a second time point when said charge reaches a chosen value, said mode control means being actuable to connect output of said charge responsive means to said terminal.