Dip carrier

Claim 2

A static shielding carrier affording mechanical support for a dual in-line packaged integrated circuit device, said carrier comprising a box-like shell formed of electrically conductive polymeric material having a bottom wall of rectangular shape, side walls, and a cover; hinge means joining said cover to one of said side walls; and wall means projecting from said bottom wall for supporting a single dual in-line packaged integrated circuit device of 300 mils and 400 mils and alternatively a single dual in-line packaged integrated circuit device of 600 mils.

Claim 3

A one-piece box-like carrier affording mechanical support and static shielding for one of a plurality of varying sized dual in-line package integrated circuit devices, said carrier comprising a box-like shell formed of electrically conductive polymeric material having a bottom wall, side walls projecting from said bottom wall, a cover, and hinge means for joining said cover and shell; and wall means projecting from said bottom wall for supporting a said dual in-line package integrated circuit device by a pair of said wall means fitting between the two rows of contacts of a said dual in-line package integrated circuit device, said wall means comprising a first pair of parallel walls having surfaces spaced 0.28 inch, a second pair of parallel walls having surfaces spaced 0.38 inch and at least one third pair of parallel walls positioned perpendicular to said first and second pairs of walls having surfaces spaced 0.58 inch.

Claim 4

A one-piece box-like carrier affording mechanical support and static shielding for one of a plurality of varying sized dual in-line package integrated circuit devices, said carrier comprising a box-like shell formed of electrically conductive polymeric material having a bottom wall, side walls projecting from said bottom wall, a cover, and hinge means for joining said cover and shell; and wall means projecting from said bottom wall for supporting a said dual in-line package integrated circuit device by a pair of said wall means fitting between the two rows of contacts of a said dual in-line package integrated circuit device, said wall means comprising a first pair of parallel walls having surfaces spaced 0.28 inch, a second pair of parallel walls having surfaces spaced 0.38 inch and at least one third pair of parallel walls positioned perpendicular to said first and second pairs of walls having surfaces spaced 0.58 inch.

Claim 5

A carrier according to claim 2 wherein each said pair of walls comprises spaced aligned wall segments.

Claim 6

A carrier according to claim 2 wherein said cover is joined along an edge perpendicular to said hinge means by frangible tabs to an adjacent cover of a second carrier.

Claim 7

A carrier according to claim 2 wherein said first pair of parallel walls comprises two walls having a length of 0.58 inch positioned generally centrally of the shell and aligned wall segments extending from opposite side walls toward said two walls; said second pair of walls comprises two walls 0.58 inch in length parallel to and spaced from said two walls of said first pair and aligned wall segments extending from said opposite side walls; and said third pair of walls comprises aligned wall segments joined to the ends of said two walls of said first pair and the ends of said two walls of said second pair.

Claim 8

A carrier according to claim 5 wherein said cover is joined along an edge perpendicular to said hinge means by frangible tabs to an adjacent cover of a second carrier.

Claim 9

A carrier according to claim 2 wherein said overall length of said shell parallel to said third pair of walls being not less than 1.65 inch and the width of said shell being at least 1.1 inch.