US4815016A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed logical circuit simulator
Assignee: Unisys Corp
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Filing: 1986-07-24
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Granted: 1989-03-21
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Expires: 2006-07-24
Abstract
Abstract An apparatus and method are provided for automatically converting a bottom-up software representation of a logical circuit design, such as created by a computer aided design (CAD) system, into a behavioral software representation which can be simulated at relatively high speed.
Inventors
- 👤 Pamela J. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:44
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
136 words
An automatic machine-implemented method for creating a stored high order software representation of a logical circuit design, said method comprising the steps of: providing a stored macrocell definition library comprised of a plurality of different macrocells, each macrocell having at least one input and one output and being represented in said library by one or more logical equations defining the logical functioning between the macrocell inputs and outputs; providing a stored bottom-up software representation of a logical circuit design comprised of macrocell connectivity data defining a predetermined connectivity between particular ones of said macrocells; and automatically converting said stored bottom-up software representation into a stored behavioral software representation comprised of a plurality of net equation representations derived by linking the logical equations corresponding to said particular ones of said macrocells as prescribed by said connectivity data.
Claim 2
Dependent Claim
136 words
An automatic machine-implemented method for creating a stored high order software representation of a logical circuit design, said method comprising the steps of: providing a stored macrocell definition library comprised of a plurality of different macrocells, each macrocell having at least one input and one output and being represented in said library by one or more logical equations defining the logical functioning between the macrocell inputs and outputs; providing a stored bottom-up software representation of a logical circuit design comprised of macrocell connectivity data defining a predetermined connectivity between particular ones of said macrocells; and automatically converting said stored bottom-up software representation into a stored behavioral software representation comprised of a plurality of net equation representations derived by linking the logical equations corresponding to said particular ones of said macrocells as prescribed by said connectivity data.
Claim 3
Dependent Claim
35 words
The invention in accordance with claim 1, wherein the step of converting includes ranking said net equation representations in an order which takes into account the evaluation sequencing thereof as indicated by said connectivity data.
Claim 4
Dependent Claim
36 words
The invention in accordance with claim 2, wherein the step of converting also includes assigning delay values to one or more logical circuit outputs so as to take into account the propagation delays of said cells.
Claim 5
Dependent Claim
24 words
The invention in accordance with claim 1, including the step of simulating the operation of said logical circuit design using said behavioral software representation.
Claim 6
Dependent Claim
23 words
The invention in accordance with claim 1, wherein said behavioral software representation produced by the step of automatically converting is a PASCAL-based representation.
Claim 7
Dependent Claim
48 words
The invention in accordance with claim 1, wherein one or more of said macrocells contain internal storage, wherein each such macrocell has a corresponding logical equation in said library for each internal state of the macrocell, and wherein said net equation representations include state equation representations derived therefrom.
Claim 8
Dependent Claim
80 words
The invention in accordance with claim 1, wherein the step of providing a stored bottom-up software representation of a logical circuit design includes providing a plurality of such stored bottom-up software representations corresponding to particular logical circuit designs along with connectivity data representative of the manner in which these particular logical circuit designs are to be interconnected, and wherein the step of automatically converting provides an overall stored behavioral software representation corresponding to the logical circuit designs and their interconnection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |