Split two-phase CCD clocking gate apparatus

Claim 1

A split two-phase CCD clocking gate apparatus comprising in combination: a substrate of P-type semiconductor material, a layer of N-type semiconductor material deposited atop said substrate, a first phase region formed in said layer of N-type semiconductor material, a virtual phase region formed in said N-type semiconductor material adjacent to and in electrical contact with said first phase region, a second phase region formed in said layer of N-type semiconductor material adjacent to and in electrical contact with said virtual phase region, a thin layer of insulating material deposited atop said layer of N-type semiconductor material covering all three regions formed in said layer of N-type semiconductor material, a first clocking gate formed on said thin layer of insulating material over said first phase region, said first clocking gate receiving a first phase clock signal, and, a second clocking gate formed on said thin layer of insulating material over said second phase region, said second clocking gate receiving a second phase clock signal, charge in the potential well in said first phase region will be transferred through said virtual phase region to the potential well in said second phase region when said first phase clock signal is repulsive and said second phase clock signal is attractive.