US4814725A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase lock circuit for compensation for bit frequency variations
Assignee: Bull HN Information Systems Italia SpA
•
Filing: 1987-10-21
•
Granted: 1989-03-21
•
Expires: 2007-10-21
Abstract
Abstract A phase lock circuit for compensation for bit frequency variations of information read from a movable magnetic media including a phase comparator, a number of low pass filters, a decoupling element and variable frequency oscillator which is temperature compensated.
Inventors
- 👤 Paolo Vitiello
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:17
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
318 words
Phase lock circuit comprising an oscillator for generating a working frequency twice the nominal recording frequency of data recorded on a magnetic media, a phase comparator having a first input for receiving periodical reading pulses of said media, a second input for receiving said working frequency, and a third input for receiving a VF0 signal having a variable frequency, said phase comparator generating a pulses positive phase error signal consisting in voltage pulses having width equal to the lag between the rising edge of each of said periodical reading pulses and a reference edge of said VF0 signal; circuit means for generating a pulsed negative phase error signal, consisting of voltage pulses having width substantially equal to the lag between said rising edge of each of said periodical reading pulses and said reference edge of said VF0 signal; an integrating filter network having a node, a first resistor having one terminal connected to said node and the other terminal connected to said phase comparator and fed by said positive phase error signal, a second resistor having one terminal connected to said node and the other terminal connected to switching means, controlled by said pulsed negative phase error signal to ground said other terminal for the duration of said negative phase pulses error signal, a first capacitor having a terminal connected to said node and the other terminal ground connected through a first compensating network comprising a compensating resistor and a compensating capacitor, parallel connected; a variable frequency oscillator for generating a periodical signal having variable frequency proportional to the voltage received at an input; and a high input impedance voltage follower having an input connected to said node and the output connected to the input of said variable frequency oscillator, the periodical signal having variable frequency generated by said variable frequency oscillator being input to said phase comparator third input and to an input of said circuit means.
Claim 2
Dependent Claim
318 words
Phase lock circuit comprising an oscillator for generating a working frequency twice the nominal recording frequency of data recorded on a magnetic media, a phase comparator having a first input for receiving periodical reading pulses of said media, a second input for receiving said working frequency, and a third input for receiving a VF0 signal having a variable frequency, said phase comparator generating a pulses positive phase error signal consisting in voltage pulses having width equal to the lag between the rising edge of each of said periodical reading pulses and a reference edge of said VF0 signal; circuit means for generating a pulsed negative phase error signal, consisting of voltage pulses having width substantially equal to the lag between said rising edge of each of said periodical reading pulses and said reference edge of said VF0 signal; an integrating filter network having a node, a first resistor having one terminal connected to said node and the other terminal connected to said phase comparator and fed by said positive phase error signal, a second resistor having one terminal connected to said node and the other terminal connected to switching means, controlled by said pulsed negative phase error signal to ground said other terminal for the duration of said negative phase pulses error signal, a first capacitor having a terminal connected to said node and the other terminal ground connected through a first compensating network comprising a compensating resistor and a compensating capacitor, parallel connected; a variable frequency oscillator for generating a periodical signal having variable frequency proportional to the voltage received at an input; and a high input impedance voltage follower having an input connected to said node and the output connected to the input of said variable frequency oscillator, the periodical signal having variable frequency generated by said variable frequency oscillator being input to said phase comparator third input and to an input of said circuit means.
Claim 3
Dependent Claim
148 words
Phase lock circuit as claimed in claim 1 wherein said oscillator comprises a frequency divider and a multiplexer controlled by at least one control signal to provide to said phase comparator, selectively, one of two working frequencies, and wherein said integrating network comprises a second capacitor having an armature connected to said node and the other armature connected to ground through a second compensating network comprising a compensating resistor and a compensating capacitor and first logic control means controlled by said control signal to disconnect from ground, in mutually exclusive way, said first or second capacitor, and wherein said variable frequency oscillator comprises a frequency divider and a multiplexer, controlled by said control signal for generating at least two variable frequency signals, one having frequency twice of the other, and for inputing to said third input of said phase comparator, selectively, one of said two variable frequency signals.
Claim 4
Dependent Claim
83 words
Phase lock circuit as claimed in claim 2 wherein said circuit means comprises a multivibrator, triggered by the rising edge of said periodical reading pulses for generating pulses having duration established by an external integrating network having at least two time constants, selectable in mutually exclusive way by said control signal and second logical means receiving in input the pulses generated by said multivibrator and a periodical signal in output from said variable frequency oscillator for generating said pulsed negative phase error signal.
Claim 5
Dependent Claim
27 words
Phase lock circuit as claimed in claim 3 wherein said external integrating network is fed by a voltage signal variable substantially as the voltage at said node.
Claim 6
Dependent Claim
53 words
Phase lock circuit as claimed in claim 4 wherein said variable frequency oscillator for generating in mutually exclusive way at least two variable frequency signals comprises an external capacitor and an external trimming resistor defining a single working range independently of the variable frequency signal selected in output from said variable frequency oscillator.
Claim 7
Dependent Claim
26 words
Phase lock circuit as claimed in claim 5 wherein said variable frequency oscillator comprises a PCT resistor for the stabilization in temperature of said working range.
References Cited (Backward Citations)
US4546330A
Cited
US4633488A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |