Super integration circuit device having a plurality of IC-chip equivalent regions formed on a single semiconductor substrate

Claim 1

A super integration circuit device comprising: a single semiconductor substrate; at least one first IC-chip equivalent region and a second IC-chip equivalent region formed on said single semiconductor substrate, each region having input and output terminals, said second IC-chip equivalent region comprising a core having predetermined patterns and preevaluated functions; a control bus for conducting output control data from an output port of said second IC-chip equivalent region to an input port of said first IC-chip equivalent region, said control bus being formed on said single semiconductor substrate, and the output control data being set to be exclusively supplied from said second IC-chip equivalent region to said at least one first IC-chip equivalent region when in a normal mode; means for directly connecting each of said IC-chip equivalent regions to a circuit external of the super-integration circuit; means, responsive to an external signal, for extracting the output control data supplied from said output port of said second IC-chip equivalent region to said input port of said at least one first IC-chip equivalent region, said extracting means including an extracting control bus having an input end connected to said control bus and having an output end connected to said extracting means, the extracting control bus being formed on said single semiconductor substrate; and an external terminal provided on said single semiconductor substrate for providing said external signal and operatively connected to said extracting means for receiving said extracted output control data, such that all ports of said first and second IC chip equivalents regions are made available at said external terminals during a test mode.