Signal processing circuit

Claim 2

A signal processing circuit comprising: constant value generating means for generating a constant value (α i ) corresponding to a delay time (d i ) for an input signal (V i (t)); adding/subtracting means for alternately adding the constant value to the input signal and subtracting the constant value from the input signal for every half period of the input signal; and amplitude correcting means for correcting an amplitude of an output signal of the adding/subtracting means for every half period of the input signal so that a delayed output signal (V o (t)) having a waveform corresponding to a waveform of the input signal is produced.

Claim 3

A signal processing circuit as claimed in claim 1, wherein the amplitude correcting means corrects the amplitude during an interval corresponding to the delay time (d i ).

Claim 4

A signal processing circuit as claimed in claim 1, wherein the amplitude correcting means comprises logic means for passing the output signal of the adding/subtracting means and producing maximum and minimum levels of the output signal of the adding/subtracting means, and adding means for alternately adding the maximum and minimum levels to the output signal of the adding/subtracting means.

Claim 5

A signal processing circuit as claimed in claim 3, wherein the logic means comprises OR circuits and low-active OR circuits each receiving the output signal of the adding/subtracting means and a timing signal for determining the interval corresponding to the delay time, and exclusive-OR circuits receiving outputs of the low-active OR circuits and the timing signal, and wherein outputs of the OR circuits and outputs of the exclusive-OR circuits are supplied to the adding means.

Claim 6

A signal processing circuit as claimed in claim 1, wherein the constant value generating means comprises exclusive-OR circuits to which a high-level signal or a low-level signal is applied to produce the constant value.

Claim 7

A signal processing circuit as claimed in claim 1, said signal processing circuit further comprises an amplitude adjusting means for setting a level of the signal from the amplitude correcting means in the vicinity of its maximum amplitude level and minimum amplitude level to the predetermined maximum and minimum levels, respectively.

Claim 8

A signal processing circuit as claimed in claim 6, wherein the amplitude adjusting means comprises first low-active OR circuits receiving the signal of the amplitude correcting means and a timing signal (UF) for designating a timing at which the signal from the amplitude correcting means is fixed to the minimum amplitude level, and wherein the amplitude adjusting means further comprises second low-active OR circuits receiving outputs of the first low-active OR circuits and a timing signal (OF) for designating a timing at which the signal from the amplitude correcting means is fixed to the maximum amplitude level.

Claim 9

A signal processing circuit as claimed in claim 1, wherein the input signal is a triangular wave signal.

Claim 10

A signal processing circuit comprising: a plurality of delay circuits connected in parallel, each delay circuit comprising constant value generating means for generating a constant value (α i ) corresponding to a delay time (d i ) for an input signal (V i (t)); adding/subtracting means for alternately adding the constant value to the input signal and subtracting the constant value from the input signal for every half period of the input signal; and amplitude correcting means for correcting an amplitude of an output signal of the adding/subtracting means for every half period of the input signal so that a delayed output signal (V o (t)) having a waveform corresponding to a waveform of the input signal is produced; and calculating means for performing a predetermined calculation for output signals from the delay circuits and the input signal (V i (t)) and extracting a signal having predetermined frequency components from the input signal.

Claim 11

A signal processing circuit comprising: a plurality of delay circuits connected in parallel, each delay circuit comprising constant value generating means for generating a constant value (α i ) corresponding to a delay time (d i ) for an input signal (V i (t)); adding/subtracting means for alternately adding the constant value to the input signal and subtracting the constant value from the input signal for every half period of the input signal; and amplitude correcting means for correcting an amplitude of an output signal of the adding/subtracting means for every half period of the input signal so that a delayed output signal (V o (t)) having a waveform corresponding to a waveform of the input signal is produced; and calculating means for performing a predetermined calculation for output signals from the delay circuits and the input signal (V i (t)) and extracting a signal having predetermined frequency components from the input signal.

Claim 12

A signal processing circuit comprising: constant value generating means for generating a constant value (α i ) corresponding to a delay time (d i ) for an input signal (V i (t)); adding means for adding the constant value to the input signal for every half period of the input signal; amplitude limiting means for limiting the level of an output signal of the adding means at a maximum level thereof and at a level larger than a minimum level thereof by a predetermined value; and a direct current level adjusting means for decreasing a direct current level of an output signal of the amplitude limiting means by a predetermined direct current value, so that the direct current level of the amplitude limiting means become equal to that of the input signal (V i (t)).

Claim 13

A signal processing circuit comprising: constant value generating means for generating a constant value (α i ) corresponding to a delay time (d i ) for an input signal (V i (t)); adding means for adding the constant value to the input signal for every half period of the input signal; amplitude limiting means for limiting the level of an output signal of the adding means at a maximum level thereof and at a level larger than a minimum level thereof by a predetermined value; and a direct current level adjusting means for decreasing a direct current level of an output signal of the amplitude limiting means by a predetermined direct current value, so that the direct current level of the amplitude limiting means become equal to that of the input signal (V i (t)).

Claim 14

A signal processing circuit as claimed in claim 10, wherein the amplitude limiting means comprises OR circuits receiving the output signal of the adding means and a carry signal of the adding means, and wherein the carry signal is produced when the adding means outputs a value exceeding the maximum level.

Claim 15

A signal processing circuit as claimed in claim 11, wherein the amplitude limiting means further comprises comparing means for comparing an output signal of the OR circuits with a predetermined level, and logic means for producing said level larger than the minimum level when the output signal of the OR circuits is smaller than the minimum level.

Claim 16

A signal processing circuit as claimed in claim 10, wherein the direct current level adjusting means comprises a subtractor for subtracting a predetermined direct current level from an output signal of the amplitude limiting means.

Claim 17

A signal processing circuit as claimed in claim 10, wherein the constant value generating means comprises low-active OR circuits each receiving a high-level signal or a low-level signal corresponding to the constant value.

Claim 18

A signal processing circuit as claimed in claim 10, wherein the input signal is a triangular wave signal.

Claim 19

A signal processing circuit comprising: a plurality of signal filtering circuits, each filtering circuit comprising constant value generating means for generating a constant value (α i ) corresponding to a delay time (d i ) for an input signal (V i (t)); adding means for adding the constant value to the input signal for every half period of the input signal; amplitude limiting means for limiting the level of an output signal of the adding means at a maximum level thereof and at a level larger than a minimum level thereof by a predetermined value; and direct current level adjusting means for decreasing a direct current level of an output signal of the amplitude limiting means by a predetermined direct current value, so that the direct current level of the amplitude limiting means becomes equal to that of the input signal (V i (t)); and calculating means for performing a predetermined calculation for output signals of the direct current adjusting means and the input signal, and producing a signal having predetermined frequency components.

Claim 20

A signal processing circuit comprising: a plurality of signal filtering circuits, each filtering circuit comprising constant value generating means for generating a constant value (α i ) corresponding to a delay time (d i ) for an input signal (V i (t)); adding means for adding the constant value to the input signal for every half period of the input signal; amplitude limiting means for limiting the level of an output signal of the adding means at a maximum level thereof and at a level larger than a minimum level thereof by a predetermined value; and direct current level adjusting means for decreasing a direct current level of an output signal of the amplitude limiting means by a predetermined direct current value, so that the direct current level of the amplitude limiting means becomes equal to that of the input signal (V i (t)); and calculating means for performing a predetermined calculation for output signals of the direct current adjusting means and the input signal, and producing a signal having predetermined frequency components.