US4811104A
Expired / Lapsed
US
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Noise eliminating apparatus for key signal
Assignee: NEC Corp
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Filing: 1987-04-14
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Granted: 1989-03-07
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Expires: 2007-04-14
Abstract
Abstract A noise eliminating apparatus, which may be used in a special effect system for a television video signal, removes noise from an input key signal by inhibiting signal transmission when the signal pulse width is below an arbitrary value. The noise eliminating apparatus includes an arbitrary value generator indicating a noise width to be eliminated. A pulse width detector produces a detection signal when the pulse width of the input key signal exceeds the noise width. A plurality of signal delay circuits are connected in series for sequentially delaying the input key signal. Associated with each delay circuit is a comparator for comparing a respective preselected constant value with the arbitary value and producing a respective coincident signal when such values coincide. A signal inhibitor, such as a logic AND gate, is associated with each delay circuit. The signal inhibitor inhibits the associated delay circuit from delaying the input key signal when the coincident signal is present but the detection signal is absent. With this arrangement, the input key signal following a removed noise signal is transmitted with unaffected width.
Inventors
- 👤 Shigehisa Kawabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:00
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
159 words
An apparatus for eliminating a noise component from an input key signal, comprising: means for generating an arbitrary value indicating a noise width to be eliminated; means for detecting the pulse width of the input key signal and producing a detection signal when the pulse width exceeds the noise width; a plurality of delay means connected in series for sequentially delaying the input key signal; means for generating a plurality of ordered values respectively associated with said plurality of delay means; a plurality of comparator means respectively associated with said plurality of delay means for comparing the arbitrary value with the respective associated ordered value and producing respective coincidence signals; and a plurality of inhibiting means respectively associated with said plurality of delay means for inhibiting transmission of the input key signal in the corresponding delay means, said inhibiting means each being responsive to a respective one of said associated coincidence signals and to lack of the detection signal.
Claim 2
Independent Claim
159 words
An apparatus for eliminating a noise component from an input key signal, comprising: means for generating an arbitrary value indicating a noise width to be eliminated; means for detecting the pulse width of the input key signal and producing a detection signal when the pulse width exceeds the noise width; a plurality of delay means connected in series for sequentially delaying the input key signal; means for generating a plurality of ordered values respectively associated with said plurality of delay means; a plurality of comparator means respectively associated with said plurality of delay means for comparing the arbitrary value with the respective associated ordered value and producing respective coincidence signals; and a plurality of inhibiting means respectively associated with said plurality of delay means for inhibiting transmission of the input key signal in the corresponding delay means, said inhibiting means each being responsive to a respective one of said associated coincidence signals and to lack of the detection signal.
Claim 3
Dependent Claim
27 words
A noise eliminating apparatus as claimed in claim 1, wherein said delay means includes a D type flip-flop and a gate controlling the setting of the flip-flop.
Claim 4
Independent Claim
133 words
An apparatus for eliminating a noise component from an input key signal, comprising: a plurality of delay means connected in series for sequentially delaying the input key signal, each said delay means including a gate; means for generating an arbitrary value corresponding to the width of a noise pulse to be removed; means for removing an inhibition to the closing of one of the gates included in said plurality of delay means in accordance with the arbitrary value; means for measuring pulse width of the input key signal and producing a detection signal when the pulse width exceeds the noise pulse width to be removed; and means for removing an inhibition to the opening of the gate closed by said closing means in response to the detection signal produced by said measuring means.
Claim 5
Independent Claim
133 words
An apparatus for eliminating a noise component from an input key signal, comprising: a plurality of delay means connected in series for sequentially delaying the input key signal, each said delay means including a gate; means for generating an arbitrary value corresponding to the width of a noise pulse to be removed; means for removing an inhibition to the closing of one of the gates included in said plurality of delay means in accordance with the arbitrary value; means for measuring pulse width of the input key signal and producing a detection signal when the pulse width exceeds the noise pulse width to be removed; and means for removing an inhibition to the opening of the gate closed by said closing means in response to the detection signal produced by said measuring means.
Claim 6
Independent Claim
183 words
An apparatus for eliminating a noise component in an input key signal, comprising: means for setting a first value corresponding to a pulse width to be eliminated as noise; means counting down clock pulses from the first value when the input key signal contains a pulse and providing a detection signal when the count reaches zero; a plurality of delay means connected in series for delaying the input key signal by units of said clock pulses; a plurality of comparator means respectively associated with said plurality of delay means, respectively, each comparator means being for comparing the first value with a respective one of a plurality of second values, the plurality of second values being predetermined in order corresponding to the serial placement of said plurality of delay means; and a plurality of gate means respectively associated with said plurality of delay means, each said gate means being disposed before the corresponding delay means to inhibit the transfer of said input key signal when a coincidence output is produced by the corresponding comparator means except when said counting means produces said detection signal.
Claim 7
Independent Claim
183 words
An apparatus for eliminating a noise component in an input key signal, comprising: means for setting a first value corresponding to a pulse width to be eliminated as noise; means counting down clock pulses from the first value when the input key signal contains a pulse and providing a detection signal when the count reaches zero; a plurality of delay means connected in series for delaying the input key signal by units of said clock pulses; a plurality of comparator means respectively associated with said plurality of delay means, respectively, each comparator means being for comparing the first value with a respective one of a plurality of second values, the plurality of second values being predetermined in order corresponding to the serial placement of said plurality of delay means; and a plurality of gate means respectively associated with said plurality of delay means, each said gate means being disposed before the corresponding delay means to inhibit the transfer of said input key signal when a coincidence output is produced by the corresponding comparator means except when said counting means produces said detection signal.
Claim 8
Dependent Claim
41 words
A noise eliminating apparatus as claimed in claim 4, wherein said plurality of second values are arranged as "0", "1", "2", and so on in correspondence with the first to the last of the series of said plurality of delay means.
Claim 9
Dependent Claim
239 words
A noise component eliminator for use in a special effect system for a television video signal for removing a noise component in an input key signal, said eliminator comprising: an input terminal for receiving an input key signal; an output terminal for delivering an output key signal; a clock generator for generating clock pulses; preset value generator means for arbitrarily generating any one of values "0", "1", and so on through "(n-1)" as a preset value; a down-counter for decrementing its count value from the preset value in response to the clock pulses during the presence of said input key signal, said down-counter delivering a detection output signal when said count value reaches zero; first, second, and so on through n-th delay circuits sequentially connected in series to transmit the input key signal from said input terminal toward said output terminal, each said delay circuit including a gate; constant value generating means for generating constant values "0", "1", and so on through "(n-1)" associated with said first, second, and so on through n-th delay circuits, respectively; and first, second, and so on through n-th comparator means associated with said first, second, and so on through n-th delay circuits, respectively, for comparing the associated constant values with said preset value to generate a coincidence signal, wherein the respective gate included in each said delay means is closed in response to said coincidence signal and lack of the detection output signal.
Claim 10
Dependent Claim
239 words
A noise component eliminator for use in a special effect system for a television video signal for removing a noise component in an input key signal, said eliminator comprising: an input terminal for receiving an input key signal; an output terminal for delivering an output key signal; a clock generator for generating clock pulses; preset value generator means for arbitrarily generating any one of values "0", "1", and so on through "(n-1)" as a preset value; a down-counter for decrementing its count value from the preset value in response to the clock pulses during the presence of said input key signal, said down-counter delivering a detection output signal when said count value reaches zero; first, second, and so on through n-th delay circuits sequentially connected in series to transmit the input key signal from said input terminal toward said output terminal, each said delay circuit including a gate; constant value generating means for generating constant values "0", "1", and so on through "(n-1)" associated with said first, second, and so on through n-th delay circuits, respectively; and first, second, and so on through n-th comparator means associated with said first, second, and so on through n-th delay circuits, respectively, for comparing the associated constant values with said preset value to generate a coincidence signal, wherein the respective gate included in each said delay means is closed in response to said coincidence signal and lack of the detection output signal.
References Cited (Backward Citations)
US4628363A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |