US4811017A
Expired / Lapsed
US
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Digital-to-analog converter
Assignee: Individual
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Filing: 1987-07-20
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Granted: 1989-03-07
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Expires: 2007-07-20
Abstract
Abstract This very high resolution digital-to-analog converter has a highest possible conversion speed as its output voltage corresponding to the input code is determined immediately. The converter has an inherent low impedance bipolar output. A digital error correction is optional. In one embodiment the converter includes at least one reference signal source and a first resistor network coupled thereto for providing a plurality of reference voltages. In response to MSBs (or LSBs), a multiplexer selects one of the reference voltages which is applied to noninverting input of an operational amplifier. A second resistor network is coupled between the inverting input and output of the operational amplifier, and has a plurality of inputs each exhibiting a respective resistance to the output of the operational amplifier. A demultiplexer couples a current source to one of the second resistor network inputs in response to LSBs (or MSBs). The conversion result is the output voltage of the operational amplifier.
Inventors
- 👤 Zdzislaw Gulczynski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:25
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/68
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
127 words
Digital-to-analog converter for converting digital input code consisting of a first and second codes of adjacent bits, into an output voltage, comprising: a pair of signal sources; a resistive means coupled between the signal sources for providing a plurality of reference voltages; a multiplexer means for selecting one of the reference voltages in response to the first code; digital-to-analog converter means having a high impedance current output for converting the second code into an output current; a resistor; and an operational amplifier having a noninverting input receiving the reference voltage selected by the multiplexer means, an inverting input receiving the output current of the digital-to-analog converter means, and an output coupled to the inverting input via the resistor for providing the output voltage of the digital-to-analog converter.
Claim 2
Dependent Claim
127 words
Digital-to-analog converter for converting digital input code consisting of a first and second codes of adjacent bits, into an output voltage, comprising: a pair of signal sources; a resistive means coupled between the signal sources for providing a plurality of reference voltages; a multiplexer means for selecting one of the reference voltages in response to the first code; digital-to-analog converter means having a high impedance current output for converting the second code into an output current; a resistor; and an operational amplifier having a noninverting input receiving the reference voltage selected by the multiplexer means, an inverting input receiving the output current of the digital-to-analog converter means, and an output coupled to the inverting input via the resistor for providing the output voltage of the digital-to-analog converter.
Claim 3
Dependent Claim
128 words
Digital-to-analog converter of claim 1, wherein the digital-to-analog converter means includes: a voltage source; a second signal source; a second resistive means coupled between the voltage source and second signal source for providing a plurality of second reference voltages; a second multiplexer means for selecting one of the second reference voltages in response to the second code; a second resistor; a second operational amplifier having a noninverting input receiving the second reference voltage selected by the second multiplexer means, an inverting input coupled to the voltage source via the second resistor, and an output; and a transistor having a source and gate coupled to the inverting input and output of the second operational amplifier respectively, and a drain for providing the output current of the digital-to-analog converter means.
Claim 4
Dependent Claim
16 words
Digital-to-analog converter of claim 1, wherein the resistive means includes equally valued resistors coupled in series.
Claim 5
Dependent Claim
52 words
Digital-to-analog converter of claim 1, wherein the input code includes least significant bits; further including means responsive to the input code for compensating the least significant bits for any inaccuracies of the digital-to-analog converter and producing a third code in response thereto, wherein the multiplexer means is responsive to the third code.
Claim 6
Dependent Claim
53 words
Digital-to-analog converter of claim 4, wherein the input code includes most significant bits, and further wherein the means for compensating includes a memory means for producing a corrective code in response to the most significant bits, and an adder for summing the corrective code and the first code and providing the third code.
Claim 7
Dependent Claim
53 words
Digital-to-analog converter of claim 1, wherein the input code includes least significant bits; further including means responsive to the input code for compensating the least significant bits for any inaccuracies of the digital-to-analog converter and producing a third code in response thereto, wherein the digital-to-analog converter means is responsive to the third code.
Claim 8
Dependent Claim
53 words
Digital-to-analog converter of claim 6, wherein the input code includes most significant bits, and further wherein the means for compensating includes a memory means for producing a corrective code in response to the most significant bits, and an adder for summing the corrective code and the second code and providing the third code.
Claim 9
Dependent Claim
155 words
Digital-to-analog converter for converting digital input code consisting of a first and second codes of adjacent bits, into an output voltage, comprising: a pair of signal sources; a first resistive means coupled between the signal sources for providing a plurality of reference voltages; a multiplexer means for selecting one of the reference voltages in response to the first code; an operational amplifier having a noninverting input receiving the reference voltage selected by the multiplexer means, an inverting input, and an output for providing the output voltage of the digital-to-analog converter; a second resistive means coupled between the inverting input and output of the operational amplifier, and having a plurality of inputs each exhibiting a respective resistance to the output of the operational amplifier; a current source means for providing a current; and a demultiplexer means for coupling the current source means to one of the second resistive means inputs in response to the second code.
Claim 10
Dependent Claim
155 words
Digital-to-analog converter for converting digital input code consisting of a first and second codes of adjacent bits, into an output voltage, comprising: a pair of signal sources; a first resistive means coupled between the signal sources for providing a plurality of reference voltages; a multiplexer means for selecting one of the reference voltages in response to the first code; an operational amplifier having a noninverting input receiving the reference voltage selected by the multiplexer means, an inverting input, and an output for providing the output voltage of the digital-to-analog converter; a second resistive means coupled between the inverting input and output of the operational amplifier, and having a plurality of inputs each exhibiting a respective resistance to the output of the operational amplifier; a current source means for providing a current; and a demultiplexer means for coupling the current source means to one of the second resistive means inputs in response to the second code.
Claim 11
Dependent Claim
81 words
Digital-to-analog converter of claim 8, wherein the current source means includes: a first and second voltage sources; a resistor; a second operational amplifier having a noninverting input coupled to the first voltage source, an inverting input coupled to the second voltage source via the resistor, and an output; and a transistor having a source and gate coupled to the inverting input and output of the second operational amplifier respectively, and a drain for providing the current of the current source means.
Claim 12
Dependent Claim
17 words
Digital-to-analog converter of claim 8, wherein the first resistive means includes equally valued resistors coupled in series.
Claim 13
Dependent Claim
17 words
Digital-to-analog converter of claim 8, wherein the second resistive means includes equally valued resistors coupled in series.
Claim 14
Dependent Claim
52 words
Digital-to-analog converter of claim 8, wherein the input code includes least significant bits; further including means responsive to the input code for compensating the least significant bits for any inaccuracies of the digital-to-analog converter and producing a third code in response thereto, wherein the multiplexer means is responsive to the third code.
Claim 15
Dependent Claim
53 words
Digital-to-analog converter of claim 12, wherein the input code includes most significant bits, and further wherein the means for compensating includes a memory means for producing a corrective code in response to the most significant bits, and an adder for summing the corrective code and the first code and providing the third code.
Claim 16
Dependent Claim
52 words
Digital-to-analog converter of claim 8, wherein the input code includes least significant bits; further including means responsive to the input code for compensating the least significant bits for any inaccuracies of the digital-to-analog converter and producing a third code in response thereto, wherein the demultiplexer means is responsive to the third code.
Claim 17
Dependent Claim
53 words
Digital-to-analog converter of claim 14, wherein the input code includes most significant bits, and further wherein the means for compensating includes a memory means for producing a corrective code in response to the most significant bits, and an adder for summing the corrective code and the second code and providing the third code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |