Logic interface circuit with high stability and low rest current

Claim 1

A logic interface circuit having a power supply rail and a common ground rail, an input terminal connectable to a source of logic signals and an output terminal for producing a replica of said logic signals, said circuit comprising a bipolar or a bipolar equivalent output transistor (T 3 ) of a first type of polarity, connected in common emitter configuration, having an emitter connected to one of said rails, a collector connected to said output terminal and a base connected to a source of a current signal for operatively driving the transistor to a condition state from a cut-off state and vice-versa a function of said logic signals, wherein said source of a current signal is an input stage which comprises a first (T 1 ) and a second (T 2 ) bipolar transistors of a second type of polarity having their respective bases connected in common to said input terminal; transistor (T 1 ) having an emitter connected to said common ground rail through a series of resistances (R 1 +R 2 ); transistor (T 2 ) having an emitter connected to said common ground rail through a series resistance (R 2 ); and a current mirror operatively connected to said power supply rail and having an input branch terminal connected to a drain of said first transistor (T 1 ) and an output branch terminal connected to a drain of said second transistor T 2 and to the base of said output transistor (T 3 ); wherein said transistor T 2 is operated at a greater current density than transistor (T 1 ); said output transistor (T 3 ) undergoing a transition from a cut-off state to a conduction stage and vice-verse whenever the signal applied to the input terminal crosses a threshold voltage (V* in ) given by the following relation; ##EQU5## where α is the ratio between the current density in said second transistor (T 2 ) and the current density in said first transistor (T 1 ),, V beT1 is the base-emitter voltage drop of said first transistor (T 1 ).