Clock injector circuit

Claim 2

Circuitry for receiving signals from at least two data busses representing distinct channels, in which each data bus provides a data stream which may be at any given time by a phase shift asynchronous with respect to that provided by the other data bus, and in which the circuitry includes a circuit for receiving the data and a circuit further responsive to the data, further characterized by: (a) an interface circuit connected to the two busses for receiving the data from the two busses, and receiving clock signals from each of said channels, the clock signals representing timing of the data on their respective busses; and (b) the interface circuit including means to transmit the data from the two busses to said circuit further responsive to the data, the means to transmit delaying said transmission for a time period approximating that of a time period represented by said phase shift.

Claim 3

Circuitry as described in claim 1, further characterized by: the means to transmit sensing the presence of data on each of the data busses and delaying transmission of the data from one of the busses until the clock signal from the other bus has changed.

Claim 4

Circuitry as described in claim 2, further characterized by: (a) the interface circuit including a pair of AND gates for one of the channels, with one AND gate being connected to an output of that channel's data bus and the other AND gate being connected to an inverted ouput of that channel's data bus, the AND gates providing their outputs to said circuit further responsive to the data as one output channel, and one of the AND gates being connected to receive the clock signals from that channel and the other one of the AND gates being connected to receive the clock signals from the other channel; and (b) the interface circuit including a second pair of AND gates for the other channel connected to an output and an inverted output of the other channel's data bus and one AND gate being connected to receive the clock signals from that channel and the other AND gate being connected to receive the clock signals from the other channel, and the AND gates providing their outputs to said circuit further responsive to the data as a second channel output.

Claim 5

Circuitry as described in claim 1, further characterized by: (a) a means for providing a master clock signal which includes a series of clock pulses (b) said means to transmit the data includes means to delay for sensing the presence of data on at least one of the data busses; and (c) said means to delay causing a reversed phase of the clock signals from one of the channels whenever the data is present on that channel and a clock pulse from said means for providing a master clock signal is sensed.

Claim 6

Circuitry as described in claim 4, further characterized by: said reversal of phase being maintained for a duration approximately equal to that of the sensed clock pulse from the master clock.

Claim 7

Circuitry as described in claim 1, further characterized by: (a) a master clock providing a signal which includes a series of clock pulses (b) said means to transmit the data includes means to delay for sensing the presence of data on each of the data busses; and (c) said means to delay causing a reversed phase of the clock signals from at least one of the channels whenever the data is present on that channel and a clock pulse from said master clock is sensed, and reversing phase of the clock signals a second time when clock signals from both channels are present.

Claim 8

Circuitry for receiving signals from at least two data busses representing distinct channels, in which each data bus provides a data stream which may be at any given time by a phase shift asynchronous with respect to that provided by the other data bus, and in which the circuitry includes a circuit for receiving the data and a circuit further responsive to the data, further characterized by: (a) an interface circuit connected to the two busses for receiving the data from the two busses, and receiving clock signals at bus clock signal rates from each of said channels, the clock signals representing timing of the data on their respective busses; (b) a master clock having a clock rate which is greater than the bus clock signal rates; and (c) the interface circuit including means to transmit the data from the two busses to said circuit further responsive to the data, the means to transmit synchronizing the data from said busses with the master clock, and further establishing a timing interval such that a reverse phase signal is generated, whereby signal changes in the data stream results in a reverse phase pulse which is shorter in duration than half of each of the clock preiods defined by the bus clock signal rates.

Claim 9

Circuitry for receiving signals from at least two data busses representing distinct channels, in which each data bus provides a data stream which may be at any given time by a phase shift asynchronous with respect to that provided by the other data bus, and in which the circuitry includes a circuit for receiving the data and a circuit further responsive to the data, further characterized by: (a) an interface circuit connected to the two busses for receiving the data from the two busses, and receiving clock signals at bus clock signal rates from each of said channels, the clock signals representing timing of the data on their respective busses; (b) a master clock having a clock rate which is greater than the bus clock signal rates; and (c) the interface circuit including means to transmit the data from the two busses to said circuit further responsive to the data, the means to transmit synchronizing the data from said busses with the master clock, and further establishing a timing interval such that a reverse phase signal is generated, whereby signal changes in the data stream results in a reverse phase pulse which is shorter in duration than half of each of the clock preiods defined by the bus clock signal rates.

Claim 10

Circuitry as defined in claim 7 further characterized by the interface circuitry including: (a) a first flip flop circuit which responds to said master clock and the data provided by the data busses to synchronize the data provided by the data busses with said master clock; (b) further flip flop circuitry, receiving the data synchronized by the first flip flop circuit, for establishing time intervals during which reverse signals are to be established in response to the synchronized data; and (c) means to provide output clock signals corresponding to the clock signals from each of the channels, delayed by said established time intervals.