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US4807010A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit in complementary circuit technology comprising a substrate bias voltage generator and a Schottky diode

Assignee: Siemens AG
•
Filing: 1986-08-11
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Granted: 1989-02-21
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Expires: 2006-08-11
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Abstract

Abstract An integrated circuit in complementary circuit technology comprising a substrate bias voltage generator which applies a negative (positive) substrate bias voltage to the p(n) substrate in which n(p) tubs are inserted. The source regions of the n(p)-channel FETs arranged in the substrate lie at ground potential. In order to avoid "latch-up" effects, an output of the substrate bias voltage generator is connected via a Schottky diode to a circuit point that lies at ground potential.

Inventors

  • 👤 Josef Winnerl
  • 👤 Dezso Takacs

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 21:56
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10D84/811; H10D89/00; H10D89/211; H10D89/213

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 161 words
An integrated circuit in complementary circuit technology, comprising: field effect transistors of different channel types and wherein at least a first field effect transistor thereof is arranged in a p-conductive semiconductor substrate and at least a second field effect transistor thereof is arranged in an n-conductive, semiconductor zone provided in said semiconductor substrate; said semiconductor zone being connected to a supply voltage; one region of said first field effect transistor being connected to a reference potential; said semiconductor substrate being connected to an output of a substrate bias voltage generator for generating a negative substrate bias voltage and to which said reference potential and said supply voltage are supplied; an n-conductive semiconductor region inserted into said semiconductor substrate and which is provided with a metal contact which forms a Schottky diode together with said n-conductive semiconductor region; said metal contact being connected to said output of said substrate bias voltage generator; and said semiconductor region being connected to said reference potential.
Claim 2
Dependent Claim 161 words
An integrated circuit in complementary circuit technology, comprising: field effect transistors of different channel types and wherein at least a first field effect transistor thereof is arranged in a p-conductive semiconductor substrate and at least a second field effect transistor thereof is arranged in an n-conductive, semiconductor zone provided in said semiconductor substrate; said semiconductor zone being connected to a supply voltage; one region of said first field effect transistor being connected to a reference potential; said semiconductor substrate being connected to an output of a substrate bias voltage generator for generating a negative substrate bias voltage and to which said reference potential and said supply voltage are supplied; an n-conductive semiconductor region inserted into said semiconductor substrate and which is provided with a metal contact which forms a Schottky diode together with said n-conductive semiconductor region; said metal contact being connected to said output of said substrate bias voltage generator; and said semiconductor region being connected to said reference potential.
Claim 3
Dependent Claim 20 words
An integrated circuit according to claim 1 wherein said metal contact is formed of a silicide of a refractory metal.
Claim 4
Dependent Claim 17 words
An integrated circuit according to claim 2 wherein the silicide of the refractory metal comprises tantalum silicide.
Claim 5
Dependent Claim 135 words
An integrated circuit in complementary circuit technology, comprising: field effect transistors of different channel types and wherein at least a first field effect transistor thereof is arranged in an n-conductive semiconductor substrate and at least a second field effect transistor thereof is arranged in a p-conductive semiconductor zone provided in said substrate; said semiconductor zone being connected to a supply voltage; one region of said first field effect transistor being connected with a reference potential; said semiconductor substrate being connected to an output of a substrate bias voltage generator for generating a substrate bias voltage and to which said reference potential and said supply voltage are provided; said semiconductor substrate being provided with a metal contact which forms a Schottky diode with said semiconductor substrate; and said metal contact being connected to said reference potential.
Claim 6
Dependent Claim 135 words
An integrated circuit in complementary circuit technology, comprising: field effect transistors of different channel types and wherein at least a first field effect transistor thereof is arranged in an n-conductive semiconductor substrate and at least a second field effect transistor thereof is arranged in a p-conductive semiconductor zone provided in said substrate; said semiconductor zone being connected to a supply voltage; one region of said first field effect transistor being connected with a reference potential; said semiconductor substrate being connected to an output of a substrate bias voltage generator for generating a substrate bias voltage and to which said reference potential and said supply voltage are provided; said semiconductor substrate being provided with a metal contact which forms a Schottky diode with said semiconductor substrate; and said metal contact being connected to said reference potential.
Claim 7
Dependent Claim 20 words
An integrated circuit according to claim 4 wherein said metal contact is formed of a silicide of a refractory metal.
Claim 8
Dependent Claim 17 words
An integrated circuit according to claim 5 wherein said silicide of a refractory metal comprises tantalum silicide.

References Cited (Backward Citations)

US4255677A Cited
US4233672A Cited
GB2054955A Cited
US4300152A Cited
US4408304A Cited
JPS58223362A Cited
US4513309A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-02-21 1992-08-22 1993-02-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-02-21 1996-08-22 1997-02-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-02-21 2000-08-22 2001-02-21 $7700.00 Window Closed / Lapsed

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