Schmitt circuit for semiconductor integrated circuit

Claim 2

A Schmitt circuit for a semiconductor integrated circuit, comprising: an input terminal for receiving an input voltage; a power source terminal for receiving a power source voltage; a first transistor having a base coupled to said input terminal, having a collector coupled to ground, and having an emitter; a second transistor having a base coupled to said emitter of said first transistor, having a collector, and having an emitter; a third transistor having a base coupled to said collector of said second transistor, having a collector and having an emitter; an output terminal coupled to said collector of said third transistor; a first resistor coupled between said power source terminal and said emitter of said first transistor, said first resistor having a constant resistance; a second resistor comprising a plurality of first resistor regions which are selectively connected between said power source terminal and said collector of said second transistor for determining a resistance of said second resistor; a third resistor comprising a plurality of second resistor regions which are selectively connected between said power source terminal and said collector of said third transistor for determining a resistance of said third resistor; a fourth resistor coupled between ground and said emitters of said second and third transistors, said fourth resistor having a constant resistance; and wiring means for selectively connecting a selected first resistor region to the power source terminal and the collector of said second transistor, and for selectively connecting a selected second resistor region to the power source terminal and the collector of said third transistor, said first and second resistor regions being selected depending on threshold voltages to be obtained in said Schmitt circuit.

Claim 3

A Schmitt circuit for a semiconductor integrated circuit as claimed in claim 1, wherein said second resistor comprises a first resistor layer and a plurality of electrodes arranged along a longitudinal direction of said first resistor layer forming said plurality of first resistor regions, wherein two selected electrodes of said plurality of electrose on said first resistor layer being terminals of said second resistor, and wherein said third resistor comprises a second resistor layer and a plurality of electrodes arranged along a longitudinal direction of said second resistor layer forming said plurality of second resistor regions, two selected electrodes of said plurality of electrodes on said second resistor layer being terminals of said third resistor.

Claim 4

A Schmitt circuit for a semiconductor integrated circuit as claimed in claim 2, wherein a single resistor layer is used in common as said first and second resistor layers, and wherein a predetermined electrode on said single resistor layer is used in common as one of said two selected electrodes on said first resistor layer and one of said two selected electrodes on said second resistor layer, and respectively connected to the power source terminal by said wiring means.

Claim 5

A Schmitt circuit for a semiconductor integrated circuit as claimed in claim 3, wherein said single resistor layer has an approximate L-shape, and wherein said predetermined electrode is located at a position where two arm portions of said L-shape meet.

Claim 6

A Schmitt circuit for a semiconductor integrated circuit as claimed in claim 1, wherein said first transistor is a PNP transistor, and wherein said second and third transistors are Schottky clamped transistors.

Claim 7

A semiconductor integrated circuit device including a Schmitt circuit comprising: an input terminal for receiving an input voltage; a power source terminal for receiving a power source voltage; a plurality of first resistor regions formed in the semiconductor device; a plurality of second resistor regions formed in the semiconductor device; a first transistor having a base coupled to said input terminal, having a collector coupled to ground and having an emitter; a second transistor having a base coupled to said emitter of said first transistor, having a collector selectively connected to said plurality of first resistor regions, and having an emitter; a third transistor having a base coupled to said collector of said second transistor, having a collector selectively connected to said plurality of second resistor regions, and having an emitter; an output terminal coupled to said collector of said third transistor; wiring means, formed on the surface of the semiconductor device, for selectively connecting said first resistor regions to said power source terminal and said collector of said second transistor, and for selectively connecting said second resistor regions to said power source terminal and said collector of said third transistor; a first resistor coupled between said power source terminal and said emitter of said first transistor, said first resistor having a constant resistance; a second resistor connected between said power source terminal and said collector of said second transistor, said resistance of said second resistor being determined by said selective connection of said first resistor regions by said wiring means; and a third resistor connected between said power source terminal and said collector of said third transistor, said resistance of said third resistor being determined by said selective connection of said second resistor regions by said wiring means.

Claim 8

A semiconductor integrated circuit device including a Schmitt circuit comprising: an input terminal for receiving an input voltage; a power source terminal for receiving a power source voltage; a plurality of first resistor regions formed in the semiconductor device; a plurality of second resistor regions formed in the semiconductor device; a first transistor having a base coupled to said input terminal, having a collector coupled to ground and having an emitter; a second transistor having a base coupled to said emitter of said first transistor, having a collector selectively connected to said plurality of first resistor regions, and having an emitter; a third transistor having a base coupled to said collector of said second transistor, having a collector selectively connected to said plurality of second resistor regions, and having an emitter; an output terminal coupled to said collector of said third transistor; wiring means, formed on the surface of the semiconductor device, for selectively connecting said first resistor regions to said power source terminal and said collector of said second transistor, and for selectively connecting said second resistor regions to said power source terminal and said collector of said third transistor; a first resistor coupled between said power source terminal and said emitter of said first transistor, said first resistor having a constant resistance; a second resistor connected between said power source terminal and said collector of said second transistor, said resistance of said second resistor being determined by said selective connection of said first resistor regions by said wiring means; and a third resistor connected between said power source terminal and said collector of said third transistor, said resistance of said third resistor being determined by said selective connection of said second resistor regions by said wiring means.

Claim 9

A Schmitt circuit as set forth in claim 1, wherein said wiring means selectively connects said first and second resistor regions in accordance with desired threshold voltages in said Schmitt circuit.